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SNJ54LVC32AW PDF预览

SNJ54LVC32AW

更新时间： 2024-11-22 22:41:03
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路输入元件
页数 文件大小 规格书
17页 521K
描述
QUADRUPLE 2-INPUT POSITIVE-OR GATES

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SNJ54LVC32AW 技术参数

生命周期：Active零件包装代码：DFP
包装说明：DFP, FL14,.25针数：14
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
Factory Lead Time：26 weeks风险等级：5.44
系列：LVC/LCX/ZJESD-30 代码：R-GDFP-F14
长度：9.21 mm负载电容（CL）：50 pF
逻辑集成电路类型：OR GATE最大I（ol）：0.024 A
功能数量：4输入次数：2
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装等效代码：FL14,.25
封装形状：RECTANGULAR封装形式：FLATPACK
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：3.8 ns传播延迟（tpd）：4.4 ns
认证状态：Not Qualified施密特触发器：NO
筛选级别：MIL-PRF-38535座面最大高度：2.03 mm
子类别：Gates最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：2.7 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.97 mm
Base Number Matches：1

SNJ54LVC32AW 数据手册

 浏览型号SNJ54LVC32AW的Datasheet PDF文件第2页浏览型号SNJ54LVC32AW的Datasheet PDF文件第3页浏览型号SNJ54LVC32AW的Datasheet PDF文件第4页浏览型号SNJ54LVC32AW的Datasheet PDF文件第5页浏览型号SNJ54LVC32AW的Datasheet PDF文件第6页浏览型号SNJ54LVC32AW的Datasheet PDF文件第7页 
SN54LVC32A, SN74LVC32A  
QUADRUPLE 2-INPUT POSITIVE-OR GATES  
www.ti.com  
SCAS286P–JANUARY 1993–REVISED APRIL 2005  
FEATURES  
•
•
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
•
Operate From 1.65 V to 3.6 V  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
•
Specified From –40°C to 85°C,  
–40°C to 125°C, and –55°C to 125°C  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
•
•
Inputs Accept Voltages to 5.5 V  
Max tpd of 3.8 ns at 3.3 V  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
– 1000-V Charged-Device Model (C101)  
SN54LVC32A . . . J OR W PACKAGE  
SN74LVC32A . . . D, DB, NS,  
OR PW PACKAGE  
SN74LVC32A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LVC32A . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1
14  
1A  
1B  
V
CC  
3
2
1
20 19  
18  
4A  
NC  
4Y  
NC  
3B  
1Y  
NC  
2A  
4
5
6
7
8
1B  
1Y  
2A  
2B  
2Y  
13 4B  
2
3
4
5
6
4B  
4A  
4Y  
3B  
3A  
3Y  
17  
16  
15  
14  
12  
11  
10  
9
4A  
4Y  
3B  
3A  
1Y  
2A  
NC  
2B  
2B  
2Y  
9 10 11 12 13  
7
8
8
GND  
NC - No internal connection  
DESCRIPTION/ORDERING INFORMATION  
The SN54LVC32A quadruple 2-input positive-OR gate is designed for 2.7-V to 3.6-V VCC operation, and the  
SN74LVC32A quadruple 2-input positive-OR gate is designed for 1.65-V to 3.6-V VCC operation.  
Y + A ) B or Y + A • B  
The 'LVC32A devices perform the Boolean function  
in positive logic.  
ORDERING INFORMATION  
ORDERABLE  
TOP-SIDE  
MARKING  
TA  
PACKAGE(1)  
Reel of 1000  
PART NUMBER  
SN74LVC32ARGYR  
SN74LVC32AD  
–40°C to 85°C  
QFN – RGY  
SOIC – D  
LC32A  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74LVC32ADR  
SN74LVC32ADT  
SN74LVC32ANSR  
SN74LVC32ADBR  
SN74LVC32APW  
SN74LVC32APWR  
SN74LVC32APWT  
SNJ54LVC32AJ  
LVC32A  
SOP – NS  
LVC32A  
LC32A  
–40°C to 125°C  
SSOP – DB  
TSSOP – PW  
LC32A  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54LVC32AJ  
SNJ54LVC32AW  
SNJ54LVC32AFK  
–55°C to 125°C  
SNJ54LVC32AW  
SNJ54LVC32AFK  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
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