SN54HCT00, SN74HCT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS062D – NOVEMBER 1988 – REVISED AUGUST 2003
Operating Voltage Range of 4.5 V to 5.5 V
Outputs Can Drive Up To 10 LSTTL Loads
Typical t = 10 ns
pd
4-mA Output Drive at 5 V
Low Power Consumption, 20-µA Max I
Low Input Current of 1 µA Max
Inputs Are TTL-Voltage Compatible
CC
SN54HCT00 . . . J OR W PACKAGE
SN74HCT00 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54HCT00 . . . FK PACKAGE
(TOP VIEW)
1A
1B
V
CC
13 4B
1
2
3
4
5
6
7
14
3
2
1
20 19
18
4A
NC
4Y
1Y
NC
2A
4
5
6
7
8
12
11
10
9
1Y
4A
4Y
3B
3A
3Y
17
16
2A
2B
15 NC
14
9 10 11 12 13
NC
2B
2Y
3B
8
GND
NC – No internal connection
description/ordering information
These devices contain four independent 2-input NAND gates. They perform the Boolean function Y = A • B or
Y = A + B in positive logic.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
SOIC – D
Tube of 25
Tube of 50
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HCT00N
SN74HCT00N
SN74HCT00D
SN74HCT00DR
SN74HCT00DT
SN74HCT00NSR
SN74HCT00DBR
SN74HCT00PW
SN74HCT00PWR
SN74HCT00PWT
SNJ54HCT00J
SNJ54HCT00W
SNJ54HCT00FK
HCT00
–40°C to 85°C
SOP – NS
HCT00
HT00
SSOP – DB
TSSOP – PW
HT00
CDIP – J
CFP – W
LCCC – FK
SNJ54HCT00J
SNJ54HCT00W
SNJ54HCT00FK
–55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
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