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SNJ54HC7032WR PDF预览

SNJ54HC7032WR

更新时间： 2024-11-25 12:58:23
品牌 Logo 应用领域
德州仪器 - TI 触发器输入元件
页数 文件大小 规格书
9页 314K
描述
HC/UH SERIES, QUAD 2-INPUT OR GATE, CDFP14, CERAMIC, DFP-14

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SNJ54HC7032WR 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：CERAMIC, DFP-14针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84Is Samacsys：N
系列：HC/UHJESD-30 代码：R-GDFP-F14
长度：9.21 mm负载电容（CL）：50 pF
逻辑集成电路类型：OR GATE功能数量：4
输入次数：2端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
传播延迟（tpd）：195 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535座面最大高度：2.03 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL宽度：6.285 mm
Base Number Matches：1

SNJ54HC7032WR 数据手册

 浏览型号SNJ54HC7032WR的Datasheet PDF文件第2页浏览型号SNJ54HC7032WR的Datasheet PDF文件第3页浏览型号SNJ54HC7032WR的Datasheet PDF文件第4页浏览型号SNJ54HC7032WR的Datasheet PDF文件第5页浏览型号SNJ54HC7032WR的Datasheet PDF文件第6页浏览型号SNJ54HC7032WR的Datasheet PDF文件第7页 
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SCLS036E − MARCH 1984 − REVISED NOVEMBER 2004  
SN54HC7032 . . . J OR W PACKAGE  
SN74HC7032 . . . D, N, OR NS PACKAGE  
(TOP VIEW)  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Operation From Very Slow Input  
Transitions  
14  
13  
12  
11  
10  
9
1A  
1B  
V
CC  
1
2
3
4
5
6
7
D
D
D
D
D
D
D
Same Pinouts as ’HC32  
4B  
4A  
4Y  
3B  
3A  
3Y  
Outputs Can Drive Up To 10 LSTTL Loads  
1Y  
Low Power Consumption, 20-µA Max I  
Typical t = 14 ns  
pd  
4-mA Output Drive at 5 V  
CC  
2A  
2B  
2Y  
8
GND  
Low Input Current of 1 µA Max  
Temperature-Compensated Threshold  
Levels  
SN54HC7032 . . . FK PACKAGE  
(TOP VIEW)  
D
High Noise Immunity  
description/ordering information  
3
2
1
20 19  
18  
4A  
NC  
4Y  
In these devices, each circuit functions as a  
quadruple OR gate. They perform the Boolean  
1Y  
NC  
2A  
4
5
6
7
8
17  
16  
Y + A • B or Y + A ) B  
function  
in positive  
15 NC  
14  
9 10 11 12 13  
NC  
2B  
logic. However, because of the Schmitt action, the  
inputs have different input threshold levels for  
positive- and negative-going signals.  
3B  
These circuits are temperature compensated and  
can be triggered from the slowest of input ramps  
and still give clean jitter-free output signals.  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PART NUMBER  
SN74HC7032N  
SN74HC7032D  
SN74HC7032DR  
SN74HC7032DT  
SN74HC7032NSR  
SNJ54HC7032J  
SNJ54HC7032W  
SNJ54HC7032FK  
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC7032N  
−40°C to 85°C  
HC7032  
SOP − NS  
CDIP − J  
HC7032  
SNJ54HC7032J  
SNJ54HC7032W  
SNJ54HC7032FK  
−55°C to 125°C  
CFP − W  
LCCC − FK  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
X
H
L
H
X
L
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
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ꢞ ꢩꢤ ꢡ ꢝ ꢧꢝ ꢡ ꢦ ꢛ ꢝꢠ ꢥꢞ ꢩꢤ ꢨ ꢛ ꢜꢤ ꢛ ꢤ ꢨꢣ ꢞ ꢠꢧ ꢕꢤꢭ ꢦꢞ ꢔꢥꢞ ꢛꢨ ꢢꢣ ꢤꢥꢛ ꢞ ꢞꢛ ꢦꢥ ꢟꢦꢨ ꢟ ꢮ ꢦꢨ ꢨ ꢦ ꢥꢛꢯꢬ  
ꢐꢨ ꢠ ꢟꢢꢡ ꢛ ꢝ ꢠꢥ ꢩꢨ ꢠ ꢡ ꢤ ꢞ ꢞ ꢝꢥ ꢰ ꢟ ꢠꢤꢞ ꢥꢠꢛ ꢥꢤ ꢡꢤ ꢞꢞ ꢦꢨ ꢝꢫ ꢯ ꢝꢥꢡ ꢫꢢꢟ ꢤ ꢛꢤ ꢞꢛ ꢝꢥꢰ ꢠꢧ ꢦꢫ ꢫ  
ꢩꢦ ꢨ ꢦ ꢣ ꢤ ꢛ ꢤ ꢨ ꢞ ꢬ  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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