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SNJ54ALS20AFK PDF预览

SNJ54ALS20AFK

更新时间: 2024-09-14 09:11:47
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路输入元件
页数 文件大小 规格书
8页 114K
描述
DUAL 4-INPUT POSITIVE-NAND GATES

SNJ54ALS20AFK 技术参数

生命周期:Active零件包装代码:QFN
包装说明:CC-20针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.57
Is Samacsys:N系列:ALS
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.0004 A功能数量:2
输入次数:4端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):1.5 mAProp。Delay @ Nom-Sup:12.5 ns
传播延迟(tpd):11 ns认证状态:Not Qualified
施密特触发器:NO筛选级别:MIL-PRF-38535
座面最大高度:2.03 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.89 mmBase Number Matches:1

SNJ54ALS20AFK 数据手册

 浏览型号SNJ54ALS20AFK的Datasheet PDF文件第2页浏览型号SNJ54ALS20AFK的Datasheet PDF文件第3页浏览型号SNJ54ALS20AFK的Datasheet PDF文件第4页浏览型号SNJ54ALS20AFK的Datasheet PDF文件第5页浏览型号SNJ54ALS20AFK的Datasheet PDF文件第6页浏览型号SNJ54ALS20AFK的Datasheet PDF文件第7页 
SN54ALS20A, SN54AS20, SN74ALS20A, SN74AS20  
DUAL 4-INPUT POSITIVE-NAND GATES  
SDAS192B – APRIL 1982 – REVISED DECEMBER 1994  
SN54ALS20A, SN54AS20 . . . J PACKAGE  
SN74ALS20A, SN74AS20 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
2D  
2C  
NC  
2B  
2A  
2Y  
description  
NC  
1C  
These devices contain two independent 4-input  
positive-NAND gates. They perform the Boolean  
functions Y = A B C D or Y = A + B + C + D  
in positive logic.  
1D  
1Y  
GND  
8
The SN54ALS20A and SN54AS20 are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS20A and SN74AS20 are characterized  
for operation from 0°C to 70°C.  
SN54ALS20A, SN54AS20 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
FUNCTION TABLE  
(each gate)  
NC  
NC  
1C  
NC  
1D  
4
5
6
7
8
2C  
NC  
NC  
NC  
2B  
17  
16  
15  
14  
INPUTS  
OUTPUT  
Y
A
H
L
B
C
H
X
X
L
D
H
X
X
X
L
H
X
L
L
9 10 11 12 13  
H
H
H
H
X
X
X
X
X
X
NC – No internal connection  
logic symbol  
logic diagram (positive logic)  
1
1
&
1A  
2
1A  
2
1B  
4
1B  
6
8
6
1Y  
2Y  
1Y  
2Y  
4
1C  
5
1C  
5
1D  
1D  
9
2A  
9
2A  
10  
2B  
8
10  
12  
2B  
2C  
12  
2C  
13  
2D  
13  
2D  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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