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SNJ54AHCT139FKR PDF预览

SNJ54AHCT139FKR

更新时间： 2024-11-04 13:13:51
品牌 Logo 应用领域
德州仪器 - TI 解码器解复用器
页数 文件大小 规格书
18页 472K
描述
AHCT/VHCT/VT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CQCC20, CERAMIC, LCC-20

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SNJ54AHCT139FKR 技术参数

生命周期：Obsolete零件包装代码：QLCC
包装说明：QCCN,针数：20
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
系列：AHCT/VHCT/VT输入调节：STANDARD
JESD-30 代码：S-CQCC-N20长度：8.89 mm
功能数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：INVERTED封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装形状：SQUARE
封装形式：CHIP CARRIER传播延迟（tpd）：10.5 ns
认证状态：Not Qualified筛选级别：MIL-PRF-38535
座面最大高度：2.03 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
宽度：8.89 mmBase Number Matches：1

SNJ54AHCT139FKR 数据手册

 浏览型号SNJ54AHCT139FKR的Datasheet PDF文件第2页浏览型号SNJ54AHCT139FKR的Datasheet PDF文件第3页浏览型号SNJ54AHCT139FKR的Datasheet PDF文件第4页浏览型号SNJ54AHCT139FKR的Datasheet PDF文件第5页浏览型号SNJ54AHCT139FKR的Datasheet PDF文件第6页浏览型号SNJ54AHCT139FKR的Datasheet PDF文件第7页 
SN54AHCT139, SN74AHCT139  
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS  
SCLS267M – DECEMBER 1995 – REVISED MARCH 2003  
SN54AHCT139 . . . J OR W PACKAGE  
SN74AHCT139 . . . D, DB, DGV, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Designed Specifically for High-Speed  
Memory Decoders and Data-Transmission  
Systems  
1G  
1A  
V
CC  
2G  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Incorporate Two Enable Inputs to Simplify  
Cascading and/or Data Reception  
1B  
2A  
1Y0  
1Y1  
1Y2  
1Y3  
GND  
2B  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
2Y0  
2Y1  
2Y2  
2Y3  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
SN54AHCT139 . . . FK PACKAGE  
(TOP VIEW)  
description/ordering information  
The ’AHCT139 devices are dual 2-line to 4-line  
decoders/demultiplexers designed for 4.5-V to  
5.5-V  
V
operation. These devices are  
CC  
3
2
1 20 19  
18  
2A  
2B  
1B  
1Y0  
NC  
4
5
6
7
8
designed to be used in high-performance  
memory-decoding or data-routing applications  
requiring very short propagation delay times. In  
high-performance memory systems, these  
decoders can be used to minimize the effects of  
system decoding. When used with high-speed  
memories utilizing a fast enable circuit, the delay  
timesofthesedecodersandtheenabletimeofthe  
memory usually are less than the typical access  
time of the memory. This means that the effective  
system delay introduced by the decoders is  
negligible.  
17  
16 NC  
15  
2Y0  
2Y1  
1Y1  
1Y2  
14  
9 10 11 12 13  
NC – No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
SOIC – D  
Tube  
SN74AHCT139N  
SN74AHCT139N  
Tube  
SN74AHCT139D  
AHCT139  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHCT139DR  
SN74AHCT139NSR  
SN74AHCT139DBR  
SN74AHCT139PW  
SN74AHCT139PWR  
SN74AHCT139DGVR  
SNJ54AHCT139J  
SNJ54AHCT139W  
SNJ54AHCT13FK  
SOP – NS  
AHCT139  
HB139  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
HB139  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
HB139  
SNJ54AHCT139J  
SNJ54AHCT139W  
SNJ54AHCT139FK  
–55°C to 125°C  
CFP – W  
Tube  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

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