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SNJ54AHCT126W PDF预览

SNJ54AHCT126W

更新时间： 2024-11-23 22:42:55
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
17页 553K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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SNJ54AHCT126W 技术参数

是否无铅： 不含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：DFP
包装说明：DFP, FL14,.3针数：14
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
Factory Lead Time：35 weeks风险等级：1.55
其他特性：DUMMY VAL控制类型：ENABLE HIGH
计数方向：UNIDIRECTIONAL系列：AHCT/VHCT/VT
JESD-30 代码：R-GDFP-F14JESD-609代码：e0
长度：9.21 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.008 A
位数：4功能数量：1
端口数量：2端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装等效代码：FL14,.3封装形状：RECTANGULAR
封装形式：FLATPACK包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
最大电源电流（ICC）：0.02 mAProp。Delay @ Nom-Sup：8.5 ns
传播延迟（tpd）：8.5 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535座面最大高度：2.03 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.285 mm

SNJ54AHCT126W 数据手册

 浏览型号SNJ54AHCT126W的Datasheet PDF文件第2页浏览型号SNJ54AHCT126W的Datasheet PDF文件第3页浏览型号SNJ54AHCT126W的Datasheet PDF文件第4页浏览型号SNJ54AHCT126W的Datasheet PDF文件第5页浏览型号SNJ54AHCT126W的Datasheet PDF文件第6页浏览型号SNJ54AHCT126W的Datasheet PDF文件第7页 
SN54AHCT126, SN74AHCT126  
QUADRUPLE BUS BUFFER GATES  
WITH 3-STATE OUTPUTS  
SCLS265O – DECEMBER 1995 – REVISED JULY 2003  
SN54AHCT126 . . . J OR W PACKAGE  
SN74AHCT126 . . . D, DB, DGV, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1OE  
1A  
V
CC  
13 4OE  
1
2
3
4
5
6
7
14  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
12  
11  
10  
9
1Y  
4A  
2OE  
2A  
4Y  
description/ordering information  
3OE  
3A  
2Y  
The ’AHCT126 devices are quadruple bus buffer  
gates featuring independent line drivers with  
3-state outputs. Each output is disabled when the  
associated output-enable (OE) input is low. When  
OE is high, the respective gate passes the data  
from the A input to its Y output.  
8
GND  
3Y  
SN54AHCT126 . . . FK PACKAGE  
(TOP VIEW)  
To ensure the high-impedance state during power  
up or power down, OE should be tied to GND  
through a pulldown resistor; the minimum value of  
the resistor is determined by the current-sourcing  
capability of the driver.  
3
2
1 20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
4
5
6
7
8
17  
16  
2OE  
NC  
15 NC  
14  
9 10 11 12 13  
3OE  
2A  
NC – No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
SOIC – D  
Tube  
SN74AHCT126N  
SN74AHCT126N  
Tube  
SN74AHCT126D  
AHCT126  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHCT126DR  
SN74AHCT126NSR  
SN74AHCT126DBR  
SN74AHCT126PW  
SN74AHCT126PWR  
SN74AHCT126DGVR  
SNJ54AHCT126J  
SNJ54AHCT126W  
SNJ54AHCT126FK  
SOP – NS  
AHCT126  
HB126  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
HB126  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
HB126  
SNJ54AHCT126J  
SNJ54AHCT126W  
SNJ54AHCT126FK  
–55°C to 125°C  
CFP – W  
Tube  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...17

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