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SNJ54AHCT00W PDF预览

SNJ54AHCT00W

更新时间: 2024-11-26 21:53:39
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路输入元件
页数 文件大小 规格书
18页 629K
描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SNJ54AHCT00W 技术参数

生命周期:Active零件包装代码:DFP
包装说明:DFP-14针数:14
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:16 weeks
风险等级:5.45Is Samacsys:N
系列:AHCT/VHCT/VTJESD-30 代码:R-GDFP-F14
长度:9.21 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.008 A
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装等效代码:FL14,.3
封装形状:RECTANGULAR封装形式:FLATPACK
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):0.02 mA
Prop。Delay @ Nom-Sup:9 ns传播延迟(tpd):9 ns
认证状态:Not Qualified施密特触发器:NO
筛选级别:MIL-PRF-38535座面最大高度:2.03 mm
子类别:Gate最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.97 mm
Base Number Matches:1

SNJ54AHCT00W 数据手册

 浏览型号SNJ54AHCT00W的Datasheet PDF文件第2页浏览型号SNJ54AHCT00W的Datasheet PDF文件第3页浏览型号SNJ54AHCT00W的Datasheet PDF文件第4页浏览型号SNJ54AHCT00W的Datasheet PDF文件第5页浏览型号SNJ54AHCT00W的Datasheet PDF文件第6页浏览型号SNJ54AHCT00W的Datasheet PDF文件第7页 
SN54AHCT00, SN74AHCT00  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
SCLS229K – OCTOBER 1995 – REVISED JULY 2003  
Inputs Are TTL-Voltage Compatible  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
SN54AHCT00 . . . J OR W PACKAGE  
SN74AHCT00 . . . D, DB, DGV, N, NS,  
OR PW PACKAGE  
SN74AHCT00 . . . RGY PACKAGE  
(TOP VIEW)  
SN54AHCT00 . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
14  
1A  
1B  
V
3
2
1
20 19  
18  
1
2
3
4
5
6
7
14  
CC  
4A  
NC  
4Y  
1Y  
NC  
2A  
4
5
6
7
8
1B  
1Y  
2A  
2B  
2Y  
13 4B  
12 4A  
2
3
4
5
6
13 4B  
17  
16  
12  
11  
10  
9
1Y  
4A  
4Y  
3B  
3A  
3Y  
11  
10  
9
4Y  
3B  
3A  
2A  
15 NC  
14  
9 10 11 12 13  
NC  
2B  
2B  
3B  
2Y  
7
8
8
GND  
NC – No internal connection  
description/ordering information  
The ’AHCT00 devices perform the Boolean function Y = A B or Y = A + B in positive logic.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
QFN – RGY  
PDIP – N  
Tape and reel  
Tube  
SN74AHCT00RGYR  
SN74AHCT00N  
HB00  
SN74AHCT00N  
Tube  
SN74AHCT00D  
SOIC – D  
AHCT00  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHCT00DR  
SN74AHCT00NSR  
SN74AHCT00DBR  
SN74AHCT00PW  
SN74AHCT00PWR  
SN74AHCT00DGVR  
SNJ54AHCT00J  
–40°C to 85°C  
SOP – NS  
AHCT00  
HB00  
SSOP – DB  
TSSOP – PW  
HB00  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
HB00  
SNJ54AHCT00J  
SNJ54AHCT00W  
SNJ54AHCT00FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHCT00W  
SNJ54AHCT00FK  
LCCC – FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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