Datasheet > 逻辑 > 总线驱动器/收发器> SNJ54ACT573W

SNJ54ACT573W

更新时间： 2024-09-09 05:04:39

品牌	Logo	应用领域
德州仪器 - TI		锁存器输出元件
页数	文件大小	规格书
16页	520K
描述
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

SNJ54ACT573W 数据手册

SN54ACT573, SN74ACT573

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS538D – OCTOBER 1995 – REVISED OCTOBER 2002

SN54ACT573 . . . J OR W PACKAGE

SN74ACT573 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

4.5-V to 5.5-V V

Operation

Inputs Accept Voltages to 5.5 V

Max t of 9.5 ns at 5 V

Inputs Are TTL-Voltage Compatible

description/ordering information

These 8-bit latches feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. The devices

are particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

GND

The eight latches are D-type transparent latches.

When the latch-enable (LE) input is high, the Q

outputs follow the data (D) inputs. When LE is

taken low, the Q outputs are latched at the logic

levels set up at the D inputs.

SN54ACT573 . . . FK PACKAGE

(TOP VIEW)

A buffered output-enable (OE) input can be used

to place the eight outputs in either a normal logic

state (high or low logic levels) or the

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines in a bus-organized system without need for

interface or pullup components.

20 19

9 10 11 12 13

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

PDIP – N

Tube

SN74ACT573N

Tube

SN74ACT573DW

SN74ACT573DWR

SN74ACT573NSR

SN74ACT573DBR

SN74ACT573PWR

SNJ54ACT573J

SOIC – DW

ACT573

Tape and reel

Tube

–40°C to 85°C

SOP – NS

SSOP – DB

TSSOP – PW

CDIP – J

ACT573

AD573

SNJ54ACT573J

SNJ54ACT573W

SNJ54ACT573FK

–55°C to 125°C

CFP – W

Tube

SNJ54ACT573W

SNJ54ACT573FK

LCCC – FK

Tube

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...16

中文翻译

下载PDF

SNJ54ACT573W 替代型号

型号	品牌	替代类型	描述	数据表
5962-8766401SA	TI	完全替代	OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

与SNJ54ACT573W相关器件

型号	品牌	获取价格	描述	数据表
SNJ54ACT574FK	TI	获取价格	OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54ACT574J	TI	获取价格	OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54ACT574W	TI	获取价格	OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54ACT74FK	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SNJ54ACT74J	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SNJ54ACT74W	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SNJ54ACT86FK	TI	获取价格	QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SNJ54ACT86J	TI	获取价格	QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SNJ54ACT86W	TI	获取价格	QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SNJ54ACT8990GB	TI	获取价格	TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES

与SNJ54ACT573W相关文章

SL74HC10N：高性能三输入与非门解析
2024-09-03

62
AIC1781A 电池充电控制器深度解析
2024-09-03

51
Pickering新高压舌簧继电器亮相汽车测试博览会
2024-08-26

84
采用MCU+MPU双处理器架构实现的创新应用设计探索
2024-08-23

94

产品中心

服务支持

精选活动

关于我们

帮助中心

SNJ54ACT573W

SNJ54ACT573W 数据手册

SNJ54ACT573W 替代型号

与SNJ54ACT573W相关器件

与SNJ54ACT573W相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SNJ54ACT573W

SNJ54ACT573W 数据手册

SNJ54ACT573W 替代型号

与SNJ54ACT573W相关器件

与SNJ54ACT573W相关文章

您还可以找

您在本页遇到什么问题？