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SNJ54ACT564W PDF预览

SNJ54ACT564W

更新时间: 2024-09-09 05:04:39
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德州仪器 - TI 触发器输出元件
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描述
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

SNJ54ACT564W 数据手册

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SN54ACT564, SN74ACT564  
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCAS549B – NOVEMBER 1995 – REVISED NOVEMBER 2002  
SN54ACT564 . . . J OR W PACKAGE  
SN74ACT564 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
4.5-V to 5.5-V V  
Operation  
CC  
Inputs Accept Voltages to 5.5 V  
Max t of 8.5 ns at 5 V  
pd  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Inputs Are TTL-Voltage Compatible  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
3-State Inverted Outputs Drive Bus Lines  
Directly  
Flow-Through Architecture to Optimize  
PCB Layout  
Full Parallel Access for Loading  
13 7Q  
12 8Q  
description/ordering information  
11  
GND  
CLK  
The ’ACT564 devices are octal D-type  
edge-triggered flip-flops that feature 3-state  
outputs designed specifically for driving highly  
capacitive or relatively low-impedance loads.  
They are particularly suitable for implementing  
buffer registers, I/O ports, bidirectional bus  
drivers, and working registers.  
SN54ACT564 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
4
5
6
7
8
3D  
4D  
5D  
6D  
7D  
2Q  
3Q  
4Q  
5Q  
6Q  
On the positive transition of the clock (CLK) input,  
the Q outputs are set to the complements of the  
logic levels set up at the data (D) inputs.  
17  
16  
15  
14  
A buffered output-enable (OE) input places the  
eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
Tube  
SN74ACT564N  
SN74ACT564N  
Tube  
SN74ACT564DW  
SN74ACT564DWR  
SN74ACT564NSR  
SN74ACT564DBR  
SN74ACT564PWR  
SNJ54ACT564J  
SOIC – DW  
ACT564  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
–40°C to 85°C  
SOP – NS  
SSOP – DB  
TSSOP – PW  
CDIP – J  
ACT564  
AD564  
AD564  
SNJ54ACT564J  
SNJ54ACT564W  
SNJ54ACT564FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54ACT564W  
SNJ54ACT564FK  
LCCC – FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES