5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SNJ54ACT563W
SNJ54ACT563W PDF预览

SNJ54ACT563W

更新时间： 2024-09-09 05:04:39
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
11页 179K
描述
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SNJ54ACT563W 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP, FL20,.3针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.56其他特性：BROADSIDE VERSION OF 533
系列：ACTJESD-30 代码：R-GDFP-F20
长度：13.09 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装等效代码：FL20,.3封装形状：RECTANGULAR
封装形式：FLATPACK包装方法：TUBE
电源：5 VProp。Delay @ Nom-Sup：14.5 ns
传播延迟（tpd）：12.5 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535座面最大高度：2.45 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
宽度：6.92 mmBase Number Matches：1

SNJ54ACT563W 数据手册

 浏览型号SNJ54ACT563W的Datasheet PDF文件第2页浏览型号SNJ54ACT563W的Datasheet PDF文件第3页浏览型号SNJ54ACT563W的Datasheet PDF文件第4页浏览型号SNJ54ACT563W的Datasheet PDF文件第5页浏览型号SNJ54ACT563W的Datasheet PDF文件第6页浏览型号SNJ54ACT563W的Datasheet PDF文件第7页 
SN54ACT563, SN74ACT563  
OCTAL D-TYPE TRANSPARENT LATCHES  
WITH 3-STATE OUTPUTS  
SCAS550B – NOVEMBER 1995 – REVISED OCTOBER 2002  
SN54ACT563 . . . J OR W PACKAGE  
SN74ACT563 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
4.5-V to 5.5-V V  
Operation  
CC  
Inputs Accept Voltages to 5.5 V  
Max t of 8.5 ns at 5 V  
pd  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Inputs Are TTL-Voltage Compatible  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
3-State Inverted Outputs Drive Bus Lines  
Directly  
Flow-Through Architecture to Optimize  
PCB Layout  
description/ordering information  
13 7Q  
12 8Q  
The ’ACT563 devices are octal D-type  
transparent latches with 3-state outputs. When  
the latch-enable (LE) input is high, the Q outputs  
are set to the complements of the data (D) inputs.  
When LE is taken low, the Q outputs are latched  
at the inverse logic levels set up at the D inputs.  
11  
GND  
LE  
SN54ACT563 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input places the  
eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased high logic  
level provide the capability to drive bus lines  
without interface or pullup components.  
3
2
1
20 19  
18  
4
5
6
7
8
3D  
4D  
5D  
6D  
7D  
2Q  
3Q  
4Q  
5Q  
6Q  
17  
16  
15  
14  
9 10 11 12 13  
OE does not affect internal operations of the  
latches. Old data can be retained or new data can  
be entered while the outputs are in the  
high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74ACT563N  
SN74ACT563N  
Tube  
SN74ACT563DW  
SN74ACT563DWR  
SN74ACT563NSR  
SN74ACT563DBR  
SN74ACT563PWR  
SNJ54ACT5634J  
SNJ54ACT563W  
SNJ54ACT563FK  
SOIC – DW  
ACT563  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
–40°C to 85°C  
SOP – NS  
SSOP – DB  
TSSOP – PW  
CDIP – J  
ACT563  
AD563  
AD563  
SNJ54ACT563J  
SNJ54ACT563W  
SNJ54ACT563FK  
–55°C to 125°C  
CFP – W  
Tube  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

中文翻译

下载PDF

与SNJ54ACT563W相关器件

型号 品牌 获取价格 描述 数据表
SNJ54ACT564FK TI

获取价格

 		OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54ACT564J TI

获取价格

 		OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54ACT564W TI

获取价格

 		OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54ACT573FK TI

获取价格

 		OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SNJ54ACT573J TI

获取价格

 		OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SNJ54ACT573W TI

获取价格

 		OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SNJ54ACT574FK TI

获取价格

 		OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54ACT574J TI

获取价格

 		OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54ACT574W TI

获取价格

 		OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54ACT74FK TI

获取价格

 		DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

与SNJ54ACT563W相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证