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SNJ54ACT563FK PDF预览

SNJ54ACT563FK

更新时间： 2024-11-09 05:04:39
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德州仪器 - TI 锁存器输出元件
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OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

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SNJ54ACT563FK 数据手册

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SN54ACT563, SN74ACT563  
OCTAL D-TYPE TRANSPARENT LATCHES  
WITH 3-STATE OUTPUTS  
SCAS550B – NOVEMBER 1995 – REVISED OCTOBER 2002  
SN54ACT563 . . . J OR W PACKAGE  
SN74ACT563 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
4.5-V to 5.5-V V  
Operation  
CC  
Inputs Accept Voltages to 5.5 V  
Max t of 8.5 ns at 5 V  
pd  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Inputs Are TTL-Voltage Compatible  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
3-State Inverted Outputs Drive Bus Lines  
Directly  
Flow-Through Architecture to Optimize  
PCB Layout  
description/ordering information  
13 7Q  
12 8Q  
The ’ACT563 devices are octal D-type  
transparent latches with 3-state outputs. When  
the latch-enable (LE) input is high, the Q outputs  
are set to the complements of the data (D) inputs.  
When LE is taken low, the Q outputs are latched  
at the inverse logic levels set up at the D inputs.  
11  
GND  
LE  
SN54ACT563 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input places the  
eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased high logic  
level provide the capability to drive bus lines  
without interface or pullup components.  
3
2
1
20 19  
18  
4
5
6
7
8
3D  
4D  
5D  
6D  
7D  
2Q  
3Q  
4Q  
5Q  
6Q  
17  
16  
15  
14  
9 10 11 12 13  
OE does not affect internal operations of the  
latches. Old data can be retained or new data can  
be entered while the outputs are in the  
high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74ACT563N  
SN74ACT563N  
Tube  
SN74ACT563DW  
SN74ACT563DWR  
SN74ACT563NSR  
SN74ACT563DBR  
SN74ACT563PWR  
SNJ54ACT5634J  
SNJ54ACT563W  
SNJ54ACT563FK  
SOIC – DW  
ACT563  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
–40°C to 85°C  
SOP – NS  
SSOP – DB  
TSSOP – PW  
CDIP – J  
ACT563  
AD563  
AD563  
SNJ54ACT563J  
SNJ54ACT563W  
SNJ54ACT563FK  
–55°C to 125°C  
CFP – W  
Tube  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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