5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SNJ54ACT373J
SNJ54ACT373J PDF预览

SNJ54ACT373J

更新时间： 2024-11-09 05:04:39
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
19页 583K
描述
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SNJ54ACT373J 技术参数

生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP20,.3针数：20
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.08控制类型：ENABLE LOW
计数方向：UNIDIRECTIONAL系列：ACT
JESD-30 代码：R-GDIP-T20长度：24.195 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.024 A位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：0.04 mA
Prop。Delay @ Nom-Sup：12.5 ns传播延迟（tpd）：12.5 ns
认证状态：Not Qualified筛选级别：MIL-PRF-38535
座面最大高度：5.08 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

SNJ54ACT373J 数据手册

 浏览型号SNJ54ACT373J的Datasheet PDF文件第2页浏览型号SNJ54ACT373J的Datasheet PDF文件第3页浏览型号SNJ54ACT373J的Datasheet PDF文件第4页浏览型号SNJ54ACT373J的Datasheet PDF文件第5页浏览型号SNJ54ACT373J的Datasheet PDF文件第6页浏览型号SNJ54ACT373J的Datasheet PDF文件第7页 
SN54ACT373, SN74ACT373  
OCTAL D-TYPE TRANSPARENT LATCHES  
WITH 3-STATE OUTPUTS  
SCAS544E – OCTOBER 1995 – REVISED OCTOBER 2002  
SN54ACT373 . . . J OR W PACKAGE  
SN74ACT373 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
4.5-V to 5.5-V V  
Operation  
CC  
Inputs Accept Voltages to 5.5 V  
Max t of 10 ns at 5 V  
pd  
Inputs Are TTL-Voltage Compatible  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
description/ordering information  
These 8-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The devices  
are particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
GND  
The eight latches are D-type transparent latches.  
When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D inputs.  
SN54ACT373 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines in bus-organized systems without need for  
interface or pullup components.  
3
2
1
20 19  
18  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74ACT373N  
SN74ACT373N  
Tube  
SN74ACT373DW  
SN74ACT373DWR  
SN74ACT373NSR  
SN74ACT373DBR  
SN74ACT373PWR  
SNJ54ACT373J  
SOIC – DW  
ACT373  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
–40°C to 85°C  
SOP – NS  
SSOP – DB  
TSSOP – PW  
CDIP – J  
ACT373  
AD373  
AD373  
SNJ54ACT373J  
SNJ54ACT373W  
SNJ54ACT373FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54ACT373W  
SNJ54ACT373FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

中文翻译

下载PDF

SNJ54ACT373J 替代型号

型号 品牌 替代类型 描述 数据表
SN74ACT373NE4 TI

类似代替

 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74ACT373N TI

类似代替

 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

与SNJ54ACT373J相关器件

型号 品牌 获取价格 描述 数据表
SNJ54ACT373W TI

获取价格

 		OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SNJ54ACT374FK TI

获取价格

 		OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54ACT374J TI

获取价格

 		OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54ACT374W TI

获取价格

 		OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54ACT534FK TI

获取价格

 		ACT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CQCC20, CERAMIC, LCC-20
SNJ54ACT5634J TI

获取价格

 		OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SNJ54ACT563FK TI

获取价格

 		OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SNJ54ACT563J TI

获取价格

 		OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SNJ54ACT563W TI

获取价格

 		OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SNJ54ACT564FK TI

获取价格

 		OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

与SNJ54ACT373J相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证