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SNJ54AC534W PDF预览

SNJ54AC534W

更新时间： 2024-11-30 05:04:39
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
15页 567K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SNJ54AC534W 数据手册

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SCAS554D − NOVEMBER 1995 − REVISED OCTOBER 2003  
SN54AC534 . . . J OR W PACKAGE  
SN74AC534 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
2-V to 6-V V  
Operation  
CC  
Inputs Accept Voltages to 6 V  
Max t of 11 ns at 5 V  
pd  
3-State Inverting Outputs Drive Bus Lines  
Directly  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
CLK  
D
Full Parallel Access for Loading  
description/ordering information  
These octal edge-triggered D-type flip-flops  
feature 3-state outputs designed specifically for  
driving  
highly  
capacitive  
or  
relatively  
low-impedance loads. The devices are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
GND  
SN54AC534 . . . FK PACKAGE  
(TOP VIEW)  
On the positive transition of the clock (CLK) input,  
the Q outputs are set to the complements of the  
logic levels set up at the data (D) inputs.  
3
2 1 20 19  
18  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without need for interface or pullup  
components.  
17  
16  
15  
14  
9 10 11 12 13  
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube  
SN74AC534N  
SN74AC534N  
Tube  
SN74AC534DW  
SN74AC534DWR  
SN74AC534NSR  
SN74AC534DBR  
SN74AC534PW  
SN74AC534PWR  
SNJ54AC534J  
SOIC − DW  
AC534  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AC534  
AC534  
−40°C to 85°C  
−55°C to 125°C  
SSOP − DB  
TSSOP − PW  
AC534  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54AC534J  
SNJ54AC534W  
SNJ54AC534FK  
Tube  
SNJ54AC534W  
SNJ54AC534FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢗ ꢁ ꢋꢌꢀꢀ ꢉ ꢊꢖ ꢌꢐꢕ ꢑꢀ ꢌ ꢁ ꢉꢊꢌꢍ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢓꢐ ꢉ ꢍ ꢗ ꢅꢊ ꢑꢉ ꢁ  
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ꢦꢣ ꢥ ꢣ ꢠ ꢡ ꢘ ꢡ ꢥ ꢛ ꢩ  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

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