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SN75LVDT1422

更新时间： 2024-01-25 13:31:16

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
20页	252K
描述
14-BIT FULL DUPLEX SERIALIZER/DESERIALIZER

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SN75LVDT1422 数据手册

SN75LVDT1422

www.ti.com

SLLS653–JUNE 2005

14-BIT FULL DUPLEX SERIALIZER/DESERIALIZER

FEATURES

•

Integrated Termination Resistor

•

10 MHz to 100 MHz Shift Clock Support

Supports Spread Spectrum Clocking

64-Pin TQFP Package (PAG)

175 Mbytes/sec In TX/RX Modes

Reduces Cable Size, Cost, and System EMI

Bidirectional Data Communication

APPLICATIONS

•

Flash Memory Cards

Plain Paper Copiers

Printers

Total Power < 360 mW Typ at 100-MHz Worst

Case Pattern

•

Power-Down Mode: < 500 µW Typ

No External Components Required for PLL

Inputs and Outputs Compatible with

TIA/EIA-644 LVDS Standard

•

ESD Rating > 5 kV (HBM)

DESCRIPTION

The SN75LVDT1422 Full Duplex Serializer/Deserializer incorporates a 14-bit serializer and a 14-bit deserializer.

Operation of the serializer is independent of the operation of the deserializer. The 14-bit serializer accepts 14

TTL input lines and generates 2 LVDS high-speed serial streams plus one LVDS clock signal. The 14-bit

deserializer accepts 3 LVDS input signals (2 high-speed serial streams and one LVDS clock signal) and drives

out 14 TTL data signals plus one TTL clock.

The serializer loads 14 data bits into registers upon the rising or falling edge of the input clock signal (CLK IN).

Rising or falling edge operation can be selected via the R/F select pin for the transmitter only. The frequency of

CLK IN is multiplied seven times and then used to unload the data registers in 7-bit slices. The two high-speed

serial streams and a phase-locked clock (TCLK±) are then output to LVDS output drivers. The frequency of

TCLK± is the same as the input clock, CLK IN.

The deserializer accepts data on two high-speed LVDS data lines. High-speed data is received and loaded into

registers at the rate seven times the LVDS input clock (RCLK±). The data is then unloaded to a 14-bit wide

LVTTL parallel bus at the RCLK± rate. The SN75LVDT1422 presents valid data on the falling edge of the output

clock (CLK OUT).

The SN75LVDT1422 provides three termination resistors for the differential LVDS inputs thus minimizing cost,

and board space, while providing better overall signal integrity (SI). The data bus appears the same at the input

to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user

interventions are as follows:

Possible use of the TX ENABLE and RX ENABLE feature. Both the TX and RX ENABLE circuits are

active-high inputs that independently enable the serializer and deserializer. When TX is disabled, the LVDS

outputs go to high impedance. When RX is disabled, the TTL outputs go to a known low state.

The SN75LVDT1422 is characterized for operation over the free-air temperature range of –10°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...20

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与SN75LVDT1422相关器件

型号	品牌	获取价格	描述	数据表
SN75LVDT1422PAG	TI	获取价格	14-BIT FULL DUPLEX SERIALIZER/DESERIALIZER
SN75LVDT1422PAGG4	TI	获取价格	14-BIT FULL DUPLEX SERIALIZER/DESERIALIZER
SN75LVDT1422PAGR	TI	获取价格	14-BIT FULL DUPLEX SERIALIZER/DESERIALIZER
SN75LVDT1422PAGRG4	TI	获取价格	14-BIT FULL DUPLEX SERIALIZER/DESERIALIZER
SN75LVDT386	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SN75LVDT386DGG	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SN75LVDT386DGGG4	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SN75LVDT386DGGR	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SN75LVDT386DGGRG4	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SN75LVDT388	TI	获取价格	HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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