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SN75LVDS32PW PDF预览

SN75LVDS32PW

更新时间： 2024-11-20 13:13:51
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
19页 314K
描述
QUAD LINE RECEIVER, PDSO16, PLASTIC, SO-16

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SN75LVDS32PW 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：TSSOP,针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.7
输入特性：DIFFERENTIAL接口集成电路类型：LINE RECEIVER
接口标准：EIA-644; TIA-644JESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
湿度敏感等级：1功能数量：4
端子数量：16最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：Not Qualified最大接收延迟：6 ns
接收器位数：4座面最大高度：1.2 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

SN75LVDS32PW 数据手册

 浏览型号SN75LVDS32PW的Datasheet PDF文件第2页浏览型号SN75LVDS32PW的Datasheet PDF文件第3页浏览型号SN75LVDS32PW的Datasheet PDF文件第4页浏览型号SN75LVDS32PW的Datasheet PDF文件第5页浏览型号SN75LVDS32PW的Datasheet PDF文件第6页浏览型号SN75LVDS32PW的Datasheet PDF文件第7页 
SN75LVDS32, SN75LVDS9637  
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS  
SLLS360B – JUNE 1999 – REVISED JUNE 2001  
Meets or Exceeds the Requirements of  
ANSI TIA/EIA-644 Standard  
SN75LVDS32D (Marked as 75LVDS32)  
SN75LVDS32PW (Marked as DS32)  
(TOP VIEW)  
Operates With a Single 3.3-V Supply  
Designed for Signaling Rate of up to  
155 Mbps  
1B  
1A  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
4B  
4A  
4Y  
G
1Y  
Differential Input Thresholds ±100 mV Max  
G
Low-Voltage TTL (LVTTL) Logic Output  
Levels  
2Y  
2A  
11 3Y  
10 3A  
Open-Circuit Fail Safe  
2B  
Characterized For Operation From  
0°C to 70°C  
GND  
9
3B  
SN75LVDS9637D (Marked as DF637 or 7L9637)  
SN75LVDS9637DGK (Marked as AXI)  
(TOP VIEW)  
description  
The SN75LVDS32 and SN75LVDS9637 are  
differential line receivers that implement the  
electricalcharacteristicsoflow-voltagedifferential  
signaling (LVDS). This signaling technique lowers  
the output voltage levels of 5-V differential  
standard levels (such as EIA/TIA-422B) to reduce  
the power, increase the switching speeds, and  
V
1
2
3
4
8
7
6
5
1A  
1B  
2A  
2B  
CC  
1Y  
2Y  
GND  
allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state  
with a ±100 mV allow operation with a differential input voltage within the input common-mode voltage range.  
The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.  
The intended application of these devices and signaling technique is both point-to-point and multidrop (one  
driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The  
transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance  
of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the  
environment.  
The SN75LVDS32 and SN75LVDS9637 are characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001 Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

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