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SN75LVDS32D PDF预览

SN75LVDS32D

更新时间： 2024-11-19 22:53:31
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
16页 217K
描述
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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SN75LVDS32D 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.47差分输出：NO
高电平输入电流最大值：0.00001 A输入特性：DIFFERENTIAL
接口集成电路类型：LINE RECEIVER接口标准：EIA-644; TIA-644
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：9.9 mm湿度敏感等级：1
功能数量：4端子数量：16
最高工作温度：70 °C最低工作温度：
最大输出低电流：0.008 A输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：6 ns接收器位数：4
座面最大高度：1.75 mm子类别：Line Driver or Receivers
最大压摆率：18 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
电源电压1-最大：3.6 V电源电压1-分钟：3 V
电源电压1-Nom：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mmBase Number Matches：1

SN75LVDS32D 数据手册

 浏览型号SN75LVDS32D的Datasheet PDF文件第2页浏览型号SN75LVDS32D的Datasheet PDF文件第3页浏览型号SN75LVDS32D的Datasheet PDF文件第4页浏览型号SN75LVDS32D的Datasheet PDF文件第5页浏览型号SN75LVDS32D的Datasheet PDF文件第6页浏览型号SN75LVDS32D的Datasheet PDF文件第7页 
SN75LVDS32, SN75LVDS9637  
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS  
SLLS360A – JUNE 1999 – REVISED MARCH 2000  
SN75LVDS32D (Marked as 75LVDS32)  
Meets or Exceeds the Requirements of  
ANSI TIA/EIA-644 Standard  
(TOP VIEW)  
Operates With a Single 3.3-V Supply  
1B  
1A  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
Designed for Signaling Rate of Up To  
155 Mbps  
4B  
4A  
4Y  
G
1Y  
G
Differential Input Thresholds ±100 mV Max  
2Y  
Low-Voltage TTL (LVTTL) Logic Output  
Levels  
2A  
11 3Y  
10 3A  
2B  
Open-Circuit Fail Safe  
GND  
9
3B  
Characterized For Operation From  
0°C to 70°C  
SN75LVDS9637D (Marked as DF637 or 7L9637)  
(TOP VIEW)  
description  
V
1A  
1B  
2A  
2B  
1
2
3
4
8
7
6
5
CC  
1Y  
The SN75LVDS32 and SN75LVDS9637 are  
differential line receivers that implement the  
electricalcharacteristicsoflow-voltagedifferential  
signaling (LVDS). This signaling technique lowers  
the output voltage levels of 5-V differential  
standard levels (such as EIA/TIA-422B) to reduce  
the power, increase the switching speeds, and  
2Y  
GND  
allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state  
with a ±100 mV allow operation with a differential input voltage within the input common-mode voltage range.  
The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.  
The intended application of these devices and signaling technique is both point-to-point and multidrop (one  
driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The  
transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance  
of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the  
environment.  
The SN75LVDS32 and SN75LVDS9637 are characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

中文翻译

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SN75LVDS32D 替代型号

型号 品牌 替代类型 描述 数据表
SN75LVDS32DR TI

类似代替

 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SN75LVDS32DG4 TI

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