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Datasheet > 驱动程序和接口 > 线路驱动器或接收器> SN75LVDM977DGG
SN75LVDM977DGG PDF预览

SN75LVDM977DGG

更新时间： 2024-11-19 22:16:11
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
28页 426K
描述
9-CHANNEL DUAL-MODE TRANSCEIVERS

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中文翻译

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SN75LVDM977DGG 技术参数

是否无铅：含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：0.50 MM PITCH, GREEN, PLASTIC, TSSOP-56针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.79Is Samacsys：N
其他特性：SUPPORTS SINGLE-ENDED AND LOW-VOLTAGE DIFFERENTIAL SCSI差分输出：YES
驱动器位数：9高电平输入电流最大值：0.00005 A
输入特性：DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型：LINE TRANSCEIVER
接口标准：X3.277; SCSI-2; SCSI-3JESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：14 mm
湿度敏感等级：2功能数量：9
端子数量：56最高工作温度：70 °C
最低工作温度：最小输出摆幅：0.9 V
最大输出低电流：0.002 A封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：5 V
认证状态：Not Qualified最大接收延迟：10 ns
接收器位数：9座面最大高度：1.2 mm
子类别：Line Driver or Receivers最大压摆率：26 mA
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED最大传输延迟：8.8 ns
宽度：6.1 mmBase Number Matches：1

SN75LVDM977DGG 数据手册

 浏览型号SN75LVDM977DGG的Datasheet PDF文件第2页浏览型号SN75LVDM977DGG的Datasheet PDF文件第3页浏览型号SN75LVDM977DGG的Datasheet PDF文件第4页浏览型号SN75LVDM977DGG的Datasheet PDF文件第5页浏览型号SN75LVDM977DGG的Datasheet PDF文件第6页浏览型号SN75LVDM977DGG的Datasheet PDF文件第7页 
SN75LVDM976, SN75LVDM977  
9-CHANNEL DUAL-MODE TRANSCEIVERS  
SLLS292B – APRIL 1998 – REVISED JANUARY 2000  
DGG PACKAGE  
(TOP VIEW)  
9 Channels for the Data and Control Paths  
of the Small Computer Systems Interface  
(SCSI)  
INV/NON  
GND  
CDE2  
CDE1  
CDE0  
9B+  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
Supports Single-Ended and Low-Voltage  
Differential (LVD) SCSI  
2
GND  
3
CMOS Input Levels (’LVDM976) or TTL  
Input Levels (’LVDM977) Available  
1A  
4
1DE/RE  
2A  
9B–  
5
Includes DIFFSENS Comparators on CDE0  
8B+  
6
2DE/RE  
3A  
8B–  
7
Single-Ended Receivers Include Noise  
Pulse Rejection Circuitry  
7B+  
8
3DE/RE  
4A  
7B–  
9
Packaged in Thin Shrink Small-Outline  
Package With 20-Mil Terminal Pitch  
6B+  
10  
11  
12  
4DE/RE  
6B–  
Low Disabled Supply Current 7 mA  
Maximum  
V
V
CC  
CC  
GND 13  
44 GND  
Power-Up/Down Glitch Protection  
GND 14  
43 GND  
Bus is High-Impedance With V  
= 1.5 V  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
GND  
GND  
GND  
GND  
GND  
GND  
CC  
Pin-Compatible With the SN75976ADGG  
High-Voltage Differential Transceiver  
V
V
CC  
5A  
CC  
description  
5B+  
5B–  
4B+  
4B–  
3B+  
3B–  
2B+  
2B–  
1B+  
1B–  
5DE/RE  
6A  
The SN75LVDM976 and SN75LVDM977 have  
nine transceivers for transmitting or receiving the  
signals to or from a SCSI data bus. They offer  
electrical compatibility to both the single-ended  
signaling of X3.277:1996–SCSI–3 Parallel Inter-  
face (Fast–20) and the new low-voltage differen-  
tial signaling method of proposed standard  
1142–D SCSI Parallel Interface – 2 (SPI–2).  
6DE/RE  
7A  
7DE/RE  
8A  
8DE/RE  
9A  
9DE/RE  
The differential drivers are nonsymmetrical. The  
SCSI bus uses a dc bias on the line to allow  
terminated fail safe and wired-OR signaling. This bias can be as high as 125 mV and induces a difference in  
the high-to-low and low-to-high transition times of a symmetrical driver. In order to reduce pulse skew, an LVD  
SCSI driver’s output characteristics become nonsymmetrical. In other words, there is more assertion current  
than negation current to or from the driver. This allows the actual differential signal voltage on the bus to be  
symmetrical about 0 V. Even though the driver output characteristics are nonsymmetrical, the design of the  
’LVDM976 drivers maintains balanced signaling. Balanced means that the current that flows in each signal line  
is nearly equal but opposite in direction and is one of the keys to the low-noise performance of a differential bus.  
AVAILABLE OPTIONS  
PACKAGE  
TSSOP  
(DGG)  
TSSOP  
(DGG)  
T
A
CMOS INPUT LEVELS  
TTL INPUTS LEVELS  
SN75LVDM976DGG  
SN75LVDM976DGGR  
SN75LVDM977DGG  
SN75LVDM977DGGR  
0°C to 70°C  
†
†
†
The R suffix designates a taped and reeled package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...28

中文翻译

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SN75LVDM977DGG 替代型号

型号 品牌 替代类型 描述 数据表
SN75LVDM977DGGRG4 TI

完全替代

 9 LINE TRANSCEIVER, PDSO56, 0.50 MM PITCH, PLASTIC, TSSOP-56
SN75LVDM977DGGR TI

完全替代

 9-CHANNEL DUAL-MODE TRANSCEIVERS

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SN75LVDM977DGGG4 TI

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SN75LVDM977DGGR TI

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 		9-CHANNEL DUAL-MODE TRANSCEIVERS
SN75LVDM977DGGRG4 TI

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 		9 LINE TRANSCEIVER, PDSO56, 0.50 MM PITCH, PLASTIC, TSSOP-56
SN75LVDM977DLG4 TI

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SN75LVDM977DLR TI

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 		9 LINE TRANSCEIVER, PDSO56, GREEN, PLASTIC, SSOP-56
SN75LVDM977DLRG4 TI

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 		9 LINE TRANSCEIVER, PDSO56, GREEN, PLASTIC, SSOP-56
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 		HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
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SN75LVDS050DG4 TI

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