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SN75LP1185CPW PDF预览

SN75LP1185CPW

更新时间: 2024-11-19 13:13:51
品牌 Logo 应用领域
德州仪器 - TI 驱动器
页数 文件大小 规格书
13页 316K
描述
LINE TRANSCEIVER, PDSO20

SN75LP1185CPW 技术参数

生命周期:Obsolete包装说明:TSSOP, TSSOP20,.25
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.69
驱动器位数:1接口集成电路类型:LINE TRANSCEIVER
接口标准:EIA-232-FJESD-30 代码:R-PDSO-G20
长度:6.5 mm标称负供电电压:-12 V
功能数量:1端子数量:20
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态:Not Qualified
接收器位数:1座面最大高度:1.2 mm
标称供电电压:5 V电源电压1-Nom:12 V
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

SN75LP1185CPW 数据手册

 浏览型号SN75LP1185CPW的Datasheet PDF文件第2页浏览型号SN75LP1185CPW的Datasheet PDF文件第3页浏览型号SN75LP1185CPW的Datasheet PDF文件第4页浏览型号SN75LP1185CPW的Datasheet PDF文件第5页浏览型号SN75LP1185CPW的Datasheet PDF文件第6页浏览型号SN75LP1185CPW的Datasheet PDF文件第7页 
SN75LP1185  
LOW-POWER MULTIPLE RS-232 DRIVERS AND RECEIVERS  
SLLS335A – JANUARY 1999 – REVISED JANUARY 2001  
DB, DW, OR N PACKAGE  
Single-Chip TIA/EIA-232-F Interface for  
IBM PC/AT Serial Port  
(TOP VIEW)  
Designed to Transmit and Receive 4-µs  
Pulses (Equivalent to 256 kbit/s)  
V
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DD  
RA1  
RA2  
RA3  
DY1  
DY2  
RA4  
DY3  
RA5  
RY1  
RY2  
RY3  
DA1  
DA2  
RY4  
DA3  
RY5  
GND  
Less Than 21-mW Power Consumption  
Wide Supply-Voltage Range . . . 4.75 V to  
15 V  
Driver Output Slew Rates Are Internally  
Controlled to 30 V/µs Max  
Receiver Input Hysteresis . . . 1000 mV  
Typical  
V
SS  
TIA/EIA-232-F Bus-Pin ESD Protection  
Exceeds:  
– 15-kV, Human-Body Model  
Three Drivers and Five Receivers Meet or  
Exceed the Requirements of TIA/EIA-232-F  
and ITU V.28  
Complements the SN75LP196  
Designed to Replace the Industry-Standard  
SN75185 and SN75C185 With the Same  
Flow-Through Pinout  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Dual-In-Line (N) Packages  
description  
The SN75LP1185 is a low-power bipolar device containing three drivers and five receivers, with 15 kV of ESD  
protection on the bus pins with respect to each other. Bus pins are defined as those pins that tie directly to the  
serial-port connector, including GND. The pinout matches the flow-through design of the industry-standard  
SN75185 and SN75C185. The flow-through pinout of the SN75LP1185 allows easy interconnection of the  
UART and serial-port connector of the IBM PC/AT and compatibles. The SN75LP1185 provides a rugged,  
low-cost solution for this function with the combination of the bipolar processing and 15 kV of ESD protection.  
The SN75LP1185 has internal slew-rate control to provide a maximum rate of change in the output signal of  
30 V/µs. The driver output swing is nominally clamped at ±6 V to enable the higher data rates associated with  
this device and to reduce EMI emissions. Even though the driver outputs are clamped, they can handle voltages  
up to ±15 V without damage. All the logic inputs can accept 3.3-V or 5-V input signals.  
The SN75LP1185 complies with the requirements of TIA/EIA-232-F and ITU V.28. These standards are for data  
interchange between a host computer and peripheral at signaling rates up to 20 kbit/s. The switching speeds  
of the SN75LP1185 support rates up to 256 kbit/s.  
The SN75LP1185 is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
IBM and PC/AT are trademarks of International Business Machines Corporation.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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