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SN75LBC086NT PDF预览

SN75LBC086NT

更新时间: 2024-01-29 04:10:25
品牌 Logo 应用领域
德州仪器 - TI 驱动器
页数 文件大小 规格书
11页 179K
描述
IC,LAN TRANSCEIVER,SINGLE,BICMOS,DIP,24PIN,PLASTIC

SN75LBC086NT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP24,.3Reach Compliance Code:not_compliant
风险等级:5.92JESD-30 代码:R-PDIP-T24
端子数量:24收发器数量:1
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP24,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
认证状态:Not Qualified子类别:Network Interfaces
最大压摆率:0.18 mA标称供电电压:5 V
表面贴装:NO技术:BICMOS
电信集成电路类型:ETHERNET TRANSCEIVER温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

SN75LBC086NT 数据手册

 浏览型号SN75LBC086NT的Datasheet PDF文件第2页浏览型号SN75LBC086NT的Datasheet PDF文件第3页浏览型号SN75LBC086NT的Datasheet PDF文件第4页浏览型号SN75LBC086NT的Datasheet PDF文件第5页浏览型号SN75LBC086NT的Datasheet PDF文件第6页浏览型号SN75LBC086NT的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ  
ꢊꢋ ꢌꢌ ꢍꢎ ꢍꢁꢏ ꢋꢐ ꢄꢑꢋ ꢒꢓ ꢑ ꢊꢎꢋꢔ ꢍꢎꢒ ꢎꢍꢆ ꢍꢋ ꢔꢍ ꢎ ꢑꢕꢐ ꢋꢎ  
ꢖ ꢋ ꢏꢗꢑ ꢀ ꢘꢙ ꢍꢄ ꢆꢗꢚ ꢑꢛ ꢐꢅ ꢅꢍꢎꢑ ꢆꢓ ꢁꢏ ꢎꢓ ꢄ ꢚꢑꢐꢁꢊ ꢑꢆꢓ ꢄ ꢄ ꢋꢀꢋ ꢓ ꢁꢑꢊ ꢍꢏ ꢍ ꢆꢏ ꢋꢓ ꢁ  
SLLS120A − JUNE 1991 − REVISED SEPTEMBER 1991  
Meets or Exceeds the IEEE STD 802.3I,  
DW PACKAGE  
(TOP VIEW)  
Type 10BASE-T  
Differential (Twisted-Pair) I/O  
CLKOUT  
X1  
1
24  
23  
22  
21  
20  
Driver/Receiver  
TXDATAA  
TXDATAB  
TXEN  
X2  
2
High-Speed Receiver . . . t = 50 ns Max  
pd  
SQEEN  
TX+  
TX−  
3
Receiver Squelch Circuit Integrity Improved  
4
With Noise Filter  
GND (L)  
5
Jabber Control Prevents Network Lockup  
V
6
19 GND (P)  
CC(L)  
7
18  
17  
16  
15  
14  
13  
GND (L)  
RXDATAA  
RXDATAB  
RXEN  
V
CC(P)  
FULLD  
Collision Detection for Multiple-User  
8
Networks  
9
RX+  
Data Link Integrity Monitored With Link  
10  
11  
12  
RX−  
Test Pulse  
LOOP  
CTL  
Externally Addressable Test Register  
LINK  
JABB  
Controls Signal Quality Error Testing  
CMOS and Raised ECL Compatible  
24-Terminal, 300-mil Dual-In-Line Package  
description  
The SN75LBC086 is a single-channel differential driver/receiver interface device for the medium attachment  
unit (MAU) used in 10-MHz twisted-pair Ethernet applications. The device uses a 5-V supply and is designed  
to interface with two pairs of telephone-grade twisted-pair cables coupled through isolation transformers. The  
functional components of the device include a differential receiver and driver, receiver squelch with noise filter,  
jabber controls, collision detection, data link monitor, and signal quality error (SQE) testing. The LinBiCMOS  
process technology is used in the device design to ensure analog precision, low power, and high-speed  
operation.  
The device contains an elaborate receiver-squelch circuit that provides an improved level of noise rejection  
by qualifying the incoming signal stream with three different criteria. First, the signal is compared to a set  
threshold voltage level. Then, the pulse duration is compared to a set time window. Last, the signal must follow  
a set pattern of positive and negative pulses before the circuit finally opens the receiver channel to the incoming  
data packet.  
The jabber control is designed to prevent a defective controller from locking up the network by limiting the data  
packet transmission time to 20 to 30 ms. When a packet length exceeds 20 to 30 ms, the driver is turned off for  
about 600 ms. The driver-enable input must be made inactive by the controller during this period before the  
jabber control will release the driver. The JABB output is active (high) when a jabber condition exists.  
Collision detection is used to arbitrate access to the multiuser network. This detection is done logically by  
monitoring the receive line for a valid signal during a driver transmission. When a collision is detected, this device  
informs the controller with an active-high CTL output. After a valid packet transmission, the device also performs  
a signal quality error test causing the CTL output to go active (high). This test is disabled when the SQEEN input  
goes inactive (high).  
The device tests data-link integrity during the idle state by periodically driving the driver line with a unipolar pulse  
called a link-test pulse. The receiver looks for this link-test pulse on the receive line. A failed line link is indicated  
by a high-impedance state at the LINK output. This output drives an LED for monitoring if needed.  
An internal test register is externally controlled with inputs FULLD and LOOP to select the device testing mode.  
When in the test mode, serial test-mode control patterns are clocked into the test register through input SQEEN.  
These control patterns select various modes to test the internal circuits.  
Embodies technology covered by one or more Digital Equipment Corporation Patents.  
LinBiCMOS is a trademark of Texas Instruments Incorporated.  
ꢏꢨ  
Copyright 1991, Texas Instruments Incorporated  
ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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