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SN751730PWR PDF预览

SN751730PWR

更新时间: 2024-01-01 21:42:21
品牌 Logo 应用领域
德州仪器 - TI 驱动器
页数 文件大小 规格书
8页 130K
描述
Triple Line Driver/Receiver 16-TSSOP

SN751730PWR 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:ObsoleteReach Compliance Code:compliant
Factory Lead Time:1 week风险等级:5.65
Is Samacsys:N接口集成电路类型:LINE TRANSCEIVER
JESD-609代码:e4湿度敏感等级:1
峰值回流温度(摄氏度):260端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

SN751730PWR 数据手册

 浏览型号SN751730PWR的Datasheet PDF文件第2页浏览型号SN751730PWR的Datasheet PDF文件第3页浏览型号SN751730PWR的Datasheet PDF文件第4页浏览型号SN751730PWR的Datasheet PDF文件第5页浏览型号SN751730PWR的Datasheet PDF文件第6页浏览型号SN751730PWR的Datasheet PDF文件第7页 
SN751730  
TRIPLE LINE DRIVER/RECEIVER  
SLLS062C – MAY 1990 – REVISED MAY 1995  
D OR N PACKAGE  
(TOP VIEW)  
Meets or Exceeds the Requirements of  
IBM 360/370 Input/Output Interface  
Specification for 4.5 Mb/s Operation  
V
DE1  
RI1  
1
2
3
4
5
6
7
8
16  
15  
14  
CC  
Single 5-V Supply  
DO1  
DI1  
Uncommited Emmitter-Follower Output  
Structure for Party-Line Operation  
RO1  
RI2  
13 DO2  
12 DI2  
Driver Output Short-Circuit Protection  
RO2  
RI3  
Driver Input/Receiver Output Compatible  
With TTL  
11  
10  
9
DO3  
DI3  
RO3  
GND  
DE2  
Receiver Input Resistance . . . 7.4 k  
to 20 kΩ  
Ratio Specification for Propagation Delay  
Time, Low-to-High/High-to-Low  
description  
TheSN751730triplelinedriver/receiverisspecificallydesignedtomeettheinput/outputinterfacespecifications  
for IBM System 360/370. It is also compatible with standard TTL logic and supply voltage levels.  
The low-impedance emitter-follower driver outputs of the SN751730 drive terminated lines such as coaxial  
cable or twisted pair. Having the outputs uncommitted allows wired-OR logic to be performed in party-line  
applications. Output short-circuit protection is provided by an internal clamping network that turns on when the  
output voltage drops below approximately 2.5 V.  
An open line affects the receiver input as does a low-level input voltage.  
All the driver inputs and receiver outputs are in conventional TTL configuration and the gating can be used  
during power-up and power-down sequences to ensure that no noise is introduced to the line by pulling either  
DE1 or DE2 to a low level.  
Function Tables  
EACH DRIVER  
INPUTS  
OUTPUT  
DO  
DI  
L
DE1  
X
DE2  
X
L
L
X
X
H
L
X
X
L
L
H
H
H
EACH DRIVER  
INPUT  
RI  
OUTPUT  
RO  
L
H
L
H
Open  
H
H = high level, L = low level,  
X = irrelevant  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
IBM is a trademark of International Business Machines Corporation.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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