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SN74S00DG4 PDF预览

SN74S00DG4

更新时间: 2024-11-26 04:13:47
品牌 Logo 应用领域
德州仪器 - TI 栅极逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
21页 738K
描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN74S00DG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:GREEN, PLASTIC, MS-012AB, SOIC-14针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.27Is Samacsys:N
系列:SJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):15 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.02 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):36 mA
Prop。Delay @ Nom-Sup:5 ns传播延迟(tpd):5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

SN74S00DG4 数据手册

 浏览型号SN74S00DG4的Datasheet PDF文件第2页浏览型号SN74S00DG4的Datasheet PDF文件第3页浏览型号SN74S00DG4的Datasheet PDF文件第4页浏览型号SN74S00DG4的Datasheet PDF文件第5页浏览型号SN74S00DG4的Datasheet PDF文件第6页浏览型号SN74S00DG4的Datasheet PDF文件第7页 
SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003  
D
Package Options Include Plastic  
Small-Outline (D, NS, PS), Shrink  
Small-Outline (DB), and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J) DIPs  
D
Also Available as Dual 2-Input  
Positive-NAND Gate in Small-Outline (PS)  
Package  
SN5400 . . . J PACKAGE  
SN54LS00, SN54S00 . . . J OR W PACKAGE  
SN7400, SN74S00 . . . D, N, OR NS PACKAGE  
SN74LS00 . . . D, DB, N, OR NS PACKAGE  
(TOP VIEW)  
SN74LS00, SN74S00 . . . PS PACKAGE  
(TOP VIEW)  
V
2B  
2A  
2Y  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1
2
3
4
8
7
6
5
1A  
1B  
1Y  
CC  
4B  
4A  
4Y  
3B  
3A  
3Y  
GND  
2Y  
GND  
8
SN5400 . . . W PACKAGE  
(TOP VIEW)  
SN54LS00, SN54S00 . . . FK PACKAGE  
(TOP VIEW)  
1A  
1B  
1Y  
4Y  
4B  
4A  
GND  
3B  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
3
2 1 20 19  
18  
4A  
NC  
4Y  
NC  
3B  
1Y  
NC  
2A  
4
5
6
7
8
V
17  
16  
15  
14  
CC  
2Y  
2A  
2B  
3A  
3Y  
NC  
2B  
8
9 10 11 12 13  
NC − No internal connection  
description/ordering information  
These devices contain four independent 2-input NAND gates. The devices perform the Boolean function  
Y = A B or Y = A + B in positive logic.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
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ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
ꢡ ꢘꢥ ꢢꢟꢟ ꢚ ꢞꢨꢢ ꢛ ꢪꢗ ꢟꢢ ꢘ ꢚꢞꢢ ꢦꢧ ꢓ ꢘ ꢝꢥ ꢥ ꢚ ꢞꢨꢢ ꢛ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢟ ꢅ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢗꢚ ꢘ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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