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SN74LVTH646IPWREP

更新时间： 2024-11-14 12:21:39
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
12页 328K
描述
3.3-V ABT OCTAL BUS TRANSVEIVER AND REGISTER WITH 3-STATE OUTPUTS

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中文翻译

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SN74LVTH646IPWREP 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：GREEN, TSSOP-24针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：8.35
Is Samacsys：N控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：LVT
JESD-30 代码：R-PDSO-G24JESD-609代码：e4
长度：7.8 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.064 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP24,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：3.5 ns传播延迟（tpd）：5.6 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：TTL
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：4.4 mmBase Number Matches：1

SN74LVTH646IPWREP 数据手册

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SCBS775A − NOVEMBER 2003 − REVISED APRIL 2004  
D
D
D
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
Enhanced Product-Change Notification  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
†
Qualification Pedigree  
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
PW PACKAGE  
(TOP VIEW)  
3.3-V V  
)
CC  
D
D
D
Supports Unregulated Battery Operation  
Down to 2.7 V  
CLKAB  
SAB  
DIR  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
V
CC  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CLKBA  
SBA  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
2
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
3
= 3.3 V, T = 25°C  
A
4
I
and Power-Up 3-State Support Hot  
off  
5
Insertion  
6
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
7
8
9
10  
11  
12  
B8  
description/ordering information  
This bus transceiver and register is designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
The SN74LVTH646 consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B  
bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input.  
Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’LVTH646.  
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the  
transceiver mode, data present at the high-impedance port can be stored in either register or in both.  
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The  
direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high),  
A data can be stored in one register and/or B data can be stored in the other register.  
When an output function is disabled, the input function is still enabled and can be used to store and transmit  
data. Only one of the two buses, A or B, can be driven at a time.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
T
A
PACKAGE  
−40°C to 85°C  
TSSOP − PW Tape and reel  
SN74LVTH646IPWREP  
LH646EP  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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SN74LVTH646IPWREP 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVTH646PWE4 TI

完全替代

 LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, PLASTIC, TSSOP-24
SN74LVTH646DGVR TI

完全替代

 LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, TVSOP-24
SN74LVTH543PWR TI

完全替代

 3.3 V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3 STATE OUTPUTS

与SN74LVTH646IPWREP相关器件

型号 品牌 获取价格 描述 数据表
SN74LVTH646NSR TI

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 		暂无描述
SN74LVTH646NSRE4 TI

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 		LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24
SN74LVTH646PW TI

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 		3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN74LVTH646PWE4 TI

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 		LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, PLASTIC, TSSOP-24
SN74LVTH646PWLE TI

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 		暂无描述
SN74LVTH646PWR TI

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 		具有三态输出的 3.3V ABT 八路总线收发器和寄存器 | PW | 24 | -40
SN74LVTH646PWRE4 TI

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 		LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, TSSOP-24
SN74LVTH646PWRG4 TI

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 		3.3-V ABT Octal Bus Transceivers And Registers With 3-State Outputs 24-TSSOP -40 to 85
SN74LVTH652 TI

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 		3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN74LVTH652DB TI

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 		3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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