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SN74LVTH573-EP PDF预览

SN74LVTH573-EP

更新时间: 2024-01-18 07:11:50
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
9页 433K
描述
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATS OUTPUTS

SN74LVTH573-EP 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:BGA包装说明:GREEN, PLASTIC, MICRO BGA-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.61Is Samacsys:N
其他特性:BROADSIDE VERSION OF 373系列:LVT
JESD-30 代码:R-PBGA-B20长度:4 mm
逻辑集成电路类型:BUS DRIVER最大I(ol):0.064 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:VFBGA
封装等效代码:BGA20,4X5,25封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:3.9 ns传播延迟(tpd):4.9 ns
认证状态:Not Qualified座面最大高度:1 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.65 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
Base Number Matches:1

SN74LVTH573-EP 数据手册

 浏览型号SN74LVTH573-EP的Datasheet PDF文件第2页浏览型号SN74LVTH573-EP的Datasheet PDF文件第3页浏览型号SN74LVTH573-EP的Datasheet PDF文件第4页浏览型号SN74LVTH573-EP的Datasheet PDF文件第5页浏览型号SN74LVTH573-EP的Datasheet PDF文件第6页浏览型号SN74LVTH573-EP的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢂ ꢉꢊ ꢋꢌ  
ꢉ ꢍꢉ ꢊꢅ ꢎꢏꢆ ꢐ ꢑꢆꢎꢄ ꢆ ꢒꢎꢁꢀ ꢌꢎꢒꢋ ꢁꢆ ꢓꢊꢆ ꢔꢌ ꢋ ꢄꢎꢆꢑ ꢇ  
ꢕ ꢖꢆ ꢇ ꢉ ꢊꢀꢆꢎꢆ ꢋ ꢐ ꢗꢆ ꢌꢗ ꢆꢀ  
SCBS773 − NOVEMBER 2003  
D
D
D
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
Enhanced Product-Change Notification  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Qualification Pedigree  
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
PW PACKAGE  
(TOP VIEW)  
3.3-V V  
)
CC  
D
D
D
Supports Unregulated Battery Operation  
Down To 2.7 V  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
1
2
3
4
5
6
7
8
9
20  
19  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
18 2Q  
17 3Q  
16 4Q  
= 3.3 V, T = 25°C  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
15  
14  
13  
12  
11  
5Q  
6Q  
7Q  
8Q  
LE  
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
GND 10  
description/ordering information  
This octal latch is designed specifically for low-voltage (3.3-V) V  
a TTL interface to a 5-V system environment.  
operation, but with the capability to provide  
CC  
The eight latches of the SN74LVTH573 are transparent D-type latches. While the latch-enable (LE) input is high,  
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set  
up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
−40°C to 85°C  
TSSOP − PW Tape and reel  
SN74LVTH573IPWREP  
LH573EP  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢆꢣ  
Copyright 2003, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢬ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢍ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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