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SN74LVTH374DWRG4 PDF预览

SN74LVTH374DWRG4

更新时间: 2024-10-02 05:24:47
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
18页 642K
描述
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

SN74LVTH374DWRG4 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:GREEN, PLASTIC, SOIC-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.23Is Samacsys:N
系列:LVTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:150000000 Hz最大I(ol):0.064 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:4.5 ns
传播延迟(tpd):5 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.5 mmBase Number Matches:1

SN74LVTH374DWRG4 数据手册

 浏览型号SN74LVTH374DWRG4的Datasheet PDF文件第2页浏览型号SN74LVTH374DWRG4的Datasheet PDF文件第3页浏览型号SN74LVTH374DWRG4的Datasheet PDF文件第4页浏览型号SN74LVTH374DWRG4的Datasheet PDF文件第5页浏览型号SN74LVTH374DWRG4的Datasheet PDF文件第6页浏览型号SN74LVTH374DWRG4的Datasheet PDF文件第7页 
ꢈ ꢋꢈ ꢌꢅ ꢍꢎꢆ ꢏ ꢐꢆꢍꢄ ꢑꢒ ꢓꢑ ꢌꢆꢔ ꢕꢓ ꢓꢑ ꢔꢑꢒ ꢒꢌꢆ ꢖꢗ ꢑ ꢘ ꢄꢕ ꢗ ꢌꢘ ꢄꢏ ꢗ  
ꢙ ꢕꢆ ꢇ ꢈ ꢌꢀꢆꢍꢆ ꢑ ꢏ ꢚꢆ ꢗ ꢚꢆ  
SCBS683H − MARCH 1997 − REVISED OCTOBER 2003  
SN54LVTH374 . . . J OR W PACKAGE  
SN74LVTH374 . . . DB, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
D
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
D
D
D
D
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OLP  
CC  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
= 3.3 V, T = 25°C  
A
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
CLK  
Support Unregulated Battery Operation  
Down to 2.7 V  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
GND  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
SN54LVTH374 . . . FK PACKAGE  
(TOP VIEW)  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
description/ordering information  
3
2
1 20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
4
5
6
7
8
These octal flip-flops are designed specifically for  
17  
16  
15  
low-voltage (3.3-V) V  
operation, but with the  
CC  
capability to provide a TTL interface to a  
5-V system environment.  
14 6D  
9 10 11 12 13  
The eight flip-flops of the ’LVTH374 devices are  
edge-triggered D-type flip-flops. On the positive  
transition of the clock (CLK) input, the Q outputs  
are set to the logic levels set up at the data (D)  
inputs.  
ORDERING INFORMATION  
ORDERABLE  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PART NUMBER  
SN74LVTH374DW  
SN74LVTH374DWR  
SN74LVTH374NSR  
SN74LVTH374DBR  
SN74LVTH374PW  
SN74LVTH374PWR  
SNJ54LVTH374J  
Tube  
SOIC − DW  
LVTH374  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
LVTH374  
LXH374  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
LXH374  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC - FK  
SNJ54LVTH374J  
SNJ54LVTH374W  
SNJ54LVTH374FK  
−55°C to 125°C  
Tube  
SNJ54LVTH374W  
SNJ54LVTH374FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢏ ꢛ ꢜ ꢝ ꢞꢟ ꢠꢡ ꢢꢣ ꢡꢞ ꢤꢜ ꢥꢦ ꢧꢛ ꢢ ꢢꢞ ꢨꢕ ꢄꢌ ꢗꢔ ꢘ ꢌꢈꢩꢂ ꢈꢂꢊ ꢧꢥꢥ ꢜꢧ ꢝ ꢧ ꢤꢪ ꢢꢪꢝ ꢣ ꢧ ꢝ ꢪ ꢢꢪ ꢣꢢꢪ ꢟ  
ꢢ ꢪ ꢣ ꢢꢦ ꢛꢭ ꢞꢯ ꢧ ꢥꢥ ꢜꢧ ꢝ ꢧ ꢤ ꢪ ꢢ ꢪ ꢝ ꢣ ꢋ  
ꢠ ꢛꢥ ꢪꢣꢣ ꢞ ꢢꢫꢪ ꢝ ꢬꢦ ꢣꢪ ꢛ ꢞꢢꢪ ꢟꢋ ꢏ ꢛ ꢧꢥ ꢥ ꢞ ꢢꢫꢪ ꢝ ꢜꢝ ꢞ ꢟꢠꢡ ꢢꢣ ꢊ ꢜꢝ ꢞ ꢟꢠꢡ ꢢꢦꢞ ꢛ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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