ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢂ ꢉꢊ ꢋꢌ
ꢉ ꢍꢉ ꢊꢅ ꢎꢏꢆ ꢐ ꢑꢆꢎꢄ ꢒꢊꢆ ꢓꢌ ꢋ ꢔ ꢄꢕ ꢌ ꢊꢔ ꢄꢐ ꢌ
ꢖ ꢕꢆꢇ ꢑ ꢄꢋ ꢎꢗ
SCBS769A − NOVEMBER 2003 − REVISED JUNE 2006
D
D
D
D
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
Enhanced Product-Change Notification
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
†
Qualification Pedigree
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
PW OR NS PACKAGE
(TOP VIEW)
3.3-V V
)
CC
D
D
D
D
D
Typical V
<0.8 V at V
(Output Ground Bounce)
= 3.3 V, T = 25°C
A
OLP
CC
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
19 8Q
1
2
3
4
5
6
7
8
9
10
20
Supports Unregulated Battery Operation
Down to 2.7 V
18 8D
Buffered Clock and Direct-Clear Inputs
Individual Data Input to Each Flip-Flop
17
7D
16
15
14
13
12
11
7Q
6Q
6D
5D
5Q
CLK
I
Supports Partial Power-Down-Mode
off
Operation
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
GND
description/ordering information
This octal D-type flip-flop is designed specifically for low-voltage (3.3 V) V
to provide a TTL interface to a 5-V system environment.
operation, but with the capability
CC
The SN74LVTH273 is a positive-edge-triggered flip-flop with a direct clear (CLR) input. Information at the data
(D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of
the clock pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition
time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal
has no effect at the output.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
−40°C to 85°C
−55°C to 125°C
TSSOP − PW
SOP − NS
Tape and reel
Tape and reel
SN74LVTH273IPWREP
SN74LVTH273MNSREP
LH273EP
LVTH273EP
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢌ
ꢌ
ꢗ
ꢐ
ꢨ
ꢒ
ꢣ
ꢘ
ꢑ
ꢡ
ꢆ
ꢢ
ꢕ
ꢜ
ꢐ
ꢚ
ꢁ
ꢛ
ꢒ
ꢎ
ꢆ
ꢎ
ꢙ
ꢚ
ꢤ
ꢛ
ꢜ
ꢢ
ꢝ
ꢞ
ꢟ
ꢟ
ꢠ
ꢠ
ꢙ
ꢙ
ꢜ
ꢜ
ꢚ
ꢚ
ꢙ
ꢡ
ꢡ
ꢥ
ꢢ
ꢣ
ꢝ
ꢝ
ꢤ
ꢤ
ꢚ
ꢠ
ꢟ
ꢞ
ꢡ
ꢡ
ꢜ
ꢛ
ꢥ
ꢆꢤ
ꢣ
ꢦ
ꢡ
ꢧ
ꢙ
ꢢ
ꢟ
ꢡ
ꢠ
ꢙ
ꢠ
ꢜ
ꢝ
ꢚ
ꢣ
ꢨ
ꢟ
ꢚ
ꢠ
ꢠ
ꢤ
ꢡ
ꢍ
Copyright 2006, Texas Instruments Incorporated
ꢝ
ꢜ
ꢢ
ꢠ
ꢜ
ꢝ
ꢞ
ꢠ
ꢜ
ꢡ
ꢥ
ꢙ
ꢛ
ꢙ
ꢢ
ꢤ
ꢝ
ꢠ
ꢩ
ꢠ
ꢤ
ꢝ
ꢜ
ꢛ
ꢪ
ꢟ
ꢕ
ꢚ
ꢞ
ꢤ
ꢡ
ꢠ
ꢟ
ꢚ
ꢨ
ꢟ
ꢝ
ꢨ
ꢫ
ꢟ
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢭ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢍ
ꢝ
ꢝ
ꢟ
ꢚ
ꢠ
ꢬ
ꢍ
ꢌ
ꢝ
ꢜ
ꢨ
ꢣ
ꢢ
ꢠ
ꢙ
ꢜ
ꢚ
ꢥ
ꢝ
ꢜ
ꢢ
ꢤ
ꢡ
ꢡ
ꢙ
ꢚ
ꢭ
ꢨ
ꢜ
ꢤ
ꢡ
ꢚ
ꢜ
ꢠ
ꢚ
ꢤ
ꢢ
ꢤ
ꢡ
ꢡ
ꢟ
ꢝ
ꢙ
ꢧ
ꢬ
ꢙ
ꢚ
ꢢ
ꢧ
ꢣ
ꢨ
ꢤ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265