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SN74LVTH241-EP PDF预览

SN74LVTH241-EP

更新时间： 2024-09-16 12:21:39
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
9页 432K
描述
3.3-V ABT OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS

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SN74LVTH241-EP 数据手册

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SCBS767 − NOVEMBER 2003  
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
D
D
D
Enhanced Product-Change Notification  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
†
Qualification Pedigree  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With 3.3-V  
V
)
CC  
D
D
Supports Unregulated Battery Operation  
Down to 2.7 V  
PW PACKAGE  
(TOP VIEW)  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
= 3.3 V, T = 25°C  
CC  
A
19 2OE  
18 1Y1  
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
17  
16  
15  
14  
13  
12  
11  
2A4  
1Y2  
2A3  
1Y3  
2A2  
1Y4  
2A1  
description/ordering information  
This octal buffer/driver is designed specifically for low-voltage (3.3-V) V  
provide a TTL interface to a 5-V system environment.  
operation, with the capability to  
CC  
The SN74LVTH241 is organized as two 4-bit line drivers with separate output-enable (1OE, 2OE) inputs. When  
1OE is low or 2OE is high, the device passes noninverted data from the A inputs to the Y outputs. When 1OE  
is high or 2OE is low, the outputs are in the high-impedance state.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
When V  
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
through a pullup resistor  
CC  
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by  
the current-sinking/current-sourcing capability of the driver.  
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the device when it is powered down. The  
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
T
A
PACKAGE  
−40°C to 85°C  
TSSOP − PW Tape and reel  
SN74LVTH241IPWREP  
LH241EP  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

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