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SN74LVTH18511DGGR PDF预览

SN74LVTH18511DGGR

更新时间： 2024-09-10 19:55:15
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
20页 273K
描述
LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PDSO64, GREEN, PLASTIC, TSSOP-64

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SN74LVTH18511DGGR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP64,.32,20
针数：64Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：8.04
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：LVTJESD-30 代码：R-PDSO-G64
长度：17 mm逻辑集成电路类型：BOUNDARY SCAN REG BUS TRANSCEIVER
最大I（ol）：0.064 A位数：9
功能数量：2端口数量：2
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP64,.32,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 VProp。Delay @ Nom-Sup：4.9 ns
传播延迟（tpd）：6.8 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：6.1 mmBase Number Matches：1

SN74LVTH18511DGGR 数据手册

 浏览型号SN74LVTH18511DGGR的Datasheet PDF文件第2页浏览型号SN74LVTH18511DGGR的Datasheet PDF文件第3页浏览型号SN74LVTH18511DGGR的Datasheet PDF文件第4页浏览型号SN74LVTH18511DGGR的Datasheet PDF文件第5页浏览型号SN74LVTH18511DGGR的Datasheet PDF文件第6页浏览型号SN74LVTH18511DGGR的Datasheet PDF文件第7页 
SN74LVTH18511  
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH BOUNDARY SCAN  
SCAS694 – MAY 2003  
DGG PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
UBT Transceiver Combines D-Type  
Latches and D-Type Flip-Flops for  
Operation in Transparent, Latched, or  
Clocked Mode  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
1CLKAB  
1LEAB  
1OEAB  
1A1  
1CLKBA  
1LEBA  
1OEBA  
1B1  
1B2  
GND  
1B3  
2
3
4
State-of-the-Art 3.3-V ABT Design Supports  
Mixed-Mode Signal Operation (5-V Input  
5
1A2  
GND  
1A3  
1A4  
1A5  
6
and Output Voltages With 3.3-V V  
)
CC  
7
Supports Unregulated Battery Operation  
Down to 2.7 V  
8
1B4  
1B5  
9
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
V
V
CC  
CC  
1A6  
1A7  
1A8  
GND  
1A9  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B6  
1B7  
1B8  
GND  
1B9  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
Compatible With the IEEE Std 1149.1-1990  
(JTAG) Test Access Port and Boundary  
Scan Architecture  
IEEE Std 1149.1-1990 Required Instructions  
and Optional CLAMP, HIGHZ, IDCODE  
description/ordering information  
The SN74LVTH18511 is an 18-bit universal bus  
transceiver with boundary scan. This device  
supports IEEE Std 1149.1-1990 boundary scan to  
facilitate testing of complex circuit-board  
assemblies. Scan access to the test circuitry is  
accomplished via the 4-wire test access port  
(TAP) interface.  
V
V
CC  
CC  
2A7  
2A8  
2A9  
GND  
2B7  
2B8  
2B9  
GND  
2OEBA  
2LEBA  
2CLKBA  
TDI  
Additionally, this device is designed specifically  
2OEAB  
2LEAB  
2CLKAB  
TDO  
for low-voltage (3.3-V) V operation, but with the  
CC  
capability to provide a TTL interface to a 5-V  
system environment.  
TMS  
TCK  
In the normal mode, this device is an 18-bit UBT  
that combines D-type latches and D-type flip-flops  
to allow data flow in transparent, latched, or clocked modes. It can be used either as two 9-bit transceivers or  
one18-bittransceiver. ActivatingtheTAPinthenormalmodedoesnotaffectthefunctionaloperationoftheUBT.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
–40°C to 85°C  
TSSOP – DGG Tape and reel  
SN74LVTH18511DGGR  
LVTH18511  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and UBT are trademarks of Texas Instruments.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...20

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