Datasheet > SN74LVTH18504APMR

SN74LVTH18504APMR

更新时间： 2024-09-11 02:58:51

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德州仪器 - TI		/
页数	文件大小	规格书
35页	528K
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3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

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SN74LVTH18504APMR 数据手册

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SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A

3.3-V ABT SCAN TEST DEVICES

WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS667B – JULY 1996 – REVISED JUNE 1997

Members of the Texas Instruments

SCOPE Family of Testability Products

Compatible With the IEEE Std 1149.1-1990

(JTAG) Test Access Port and

Boundary-Scan Architecture

Members of the Texas Instruments

Widebus Family

SCOPE Instruction Set

– IEEE Std 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ

– Parallel-Signature Analysis at Inputs

– Pseudo-Random Pattern Generation

From Outputs

State-of-the-Art 3.3-V ABT Design Supports

Mixed-Mode Signal Operation (5-V Input

and Output Voltages With 3.3-V V

)

Support Unregulated Battery Operation

Down to 2.7 V

UBT (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Device Identification

– Even-Parity Opcodes

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

Packaged in 64-Pin Plastic Thin Quad Flat

(PM) Packages Using 0.5-mm

Center-to-Center Spacings and 68-Pin

Ceramic Quad Flat (HV) Packages Using

25-mil Center-to-Center Spacings

B-Port Outputs of ’LVTH182504A Devices

Have Equivalent 25-Ω Series Resistors, So

No External Resistors Are Required

description

The ’LVTH18504A and ’LVTH182504A scan test devices with 20-bit universal bus transceivers are members

of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices supports

IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to

the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) V

capability to provide a TTL interface to a 5-V system environment.

operation, but with the

In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type

flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the

TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the

boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the

SCOPE universal bus transceivers.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),

clock-enable (CLKENAB and CLKENBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the

device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while

CLKENAB is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and

CLKENAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs

are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to

A-to-B data flow, but uses the OEBA, LEBA, CLKENBA, and CLKBA inputs.

Inthetestmode, thenormaloperationoftheSCOPEuniversalbustransceiversisinhibited, andthetestcircuitry

is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs

boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE, UBT, and Widebus are trademarks of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...35

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SN74LVTH18504APMR 替代型号

型号	品牌	替代类型	描述	数据表
SN74LVTH18504APMG4	TI	完全替代	3.3-V ABT Scan Test Devices With 20-Bit Universal Bus Transceivers 64-LQFP -40 to 85
SN74LVTH18504APM	TI	完全替代	3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

与SN74LVTH18504APMR相关器件

型号	品牌	获取价格	描述	数据表
SN74LVTH18511DGGR	TI	获取价格	LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PDSO64, GREEN, PLASTIC,
SN74LVTH18512	TI	获取价格	3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SN74LVTH18512DGG	TI	获取价格	3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SN74LVTH18512DGGR	TI	获取价格	3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SN74LVTH18514	TI	获取价格	3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN74LVTH18514DGG	TI	获取价格	3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN74LVTH18514DGGR	TI	获取价格	3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SN74LVTH18640DGGR	TI	获取价格	LVT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, INVERTED OUTPUT, PDSO56
SN74LVTH18640DL	TI	获取价格	LVT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, INVERTED OUTPUT, PDSO56
SN74LVTH18640DLR	TI	获取价格	LVT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, INVERTED OUTPUT, PDSO56

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