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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004
D
D
D
D
D
D
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup Resistors
Enhanced Product-Change Notification
B-Port Outputs of SN74LVTH182502A
Device Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required
†
Qualification Pedigree
Members of the Texas Instruments
SCOPE Family of Testability Products
Members of the Texas Instruments
Widebus Family
State-of-the-Art 3.3-V ABT Design Supports
Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V V
D
D
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
SCOPE Instruction Set
)
CC
− IEEE Standard 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
D
Support Unregulated Battery Operation
Down to 2.7 V
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
− Parallel-Signature Analysis at Inputs
− Pseudorandom Pattern Generation From
Outputs
− Sample Inputs/Toggle Outputs
− Binary Count From Outputs
− Device Identification
− Even-Parity Opcodes
description/ordering information
The SN74LVTH18502A and SN74LVTH182502A scan test devices, with 18-bit universal bus transceivers, are
members of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports
IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan
access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
Additionally, these devices are designed specifically for low-voltage (3.3-V) V
capability to provide a TTL interface to a 5-V system environment.
operation, but with the
CC
In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type
flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit
transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples
of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP
in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
T
A
PACKAGE
LQFP − PM
LQFP − PM
Tape and reel
Tape and reel
8V18502AIPMREP
LH18502AEP
−40°C to 85°C
§
8V182502AIPMREP
‡
§
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
Product Preview
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE, Widebus, and UBT are trademarks of Texas Instruments.
Copyright 2004, Texas Instruments Incorporated
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