SN54LVTH16244A, SN74LVTH16244B
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS142M – MAY 1992 – REVISED MARCH 2000
SN54LVTH16244A . . . WD PACKAGE
SN74LVTH16244B . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Y1
1Y2
GND
1Y3
1Y4
2OE
1A1
1A2
GND
1A3
1A4
2
3
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
4
5
3.3-V V
)
CC
6
Support Unregulated Battery Operation
Down to 2.7 V
7
V
V
CC
CC
8
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
9
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
= 3.3 V, T = 25°C
A
I
and Power-Up 3-State Support Hot
off
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
V
V
CC
CC
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
4Y1
4Y2
GND
4Y3
4Y4
4A1
4A2
GND
4A3
4A4
3OE
– 1000-V Charged-Device Model (C101)
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
4OE
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The SN54LVTH16244A and SN74LVTH16244B devices are 16-bit buffers and line drivers designed for
low-voltage (3.3-V) V operation, but with the capability to provide a TTL interface to a 5-V system
CC
environment. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These
devices provide true outputs and symmetrical active-low output-enable (OE) inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V is between 0 and 1.5-V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5-V, OE should be tied to V
through a pullup resistor;
CC
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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