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SN74LVTH162373-EP

更新时间： 2024-09-10 12:21:39
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德州仪器 - TI 锁存器输出元件
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10页 285K
描述
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74LVTH162373-EP 数据手册

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SN74LVTH162373-EP  
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS811A–JULY 2006–REVISED JULY 2006  
FEATURES  
•
Controlled Baseline  
•
•
•
Flow-Through Architecture Optimizes PCB  
Layout  
– One Assembly/Test Site, One Fabrication  
Site  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
•
•
Extended Temperature Performance of –55°C  
to 125°C  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
xxxxxxxxxxxx  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
•
•
•
Enhanced Product-Change Notification  
(1)  
Qualification Pedigree  
DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments Widebus™  
Family  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
VCC  
1Q5  
1Q6  
1
2
3
4
5
6
7
8
9
48 1LE  
47 1D1  
•
Output Ports Have Equivalent 22-Ω Series  
Resistors, So No External Resistors Are  
Required  
46  
1D2  
45 GND  
44 1D3  
•
•
•
•
•
•
Supports Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V VCC  
)
43  
1D4  
42 VCC  
41 1D5  
40 1D6  
39 GND  
38 1D7  
37 1D8  
Supports Unregulated Battery Operation  
Down to 2.7 V  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
GND 10  
1Q7  
1Q8  
11  
12  
Ioff and Power-Up 3-State Support Hot  
Insertion  
2Q1 13  
2Q2  
36  
2D1  
14  
35 2D2  
34 GND  
33 2D3  
32 2D4  
31 VCC  
30 2D5  
29 2D6  
28 GND  
27 2D7  
26 2D8  
25 2LE  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
GND 15  
2Q3 16  
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
2Q4  
17  
VCC 18  
2Q5 19  
2Q6 20  
GND 21  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
2Q7  
22  
2Q8 23  
2OE 24  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
xxxx  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVTH162373 is a 16-bit transparent D-type latch with 3-state outputs designed for low-voltage (3.3-V)  
VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. This device is  
particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
LVTH162373EP  
–55°C to 125°C  
SSOP – DL  
Tape and reel  
CLVTH162373MDLREP  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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