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SN74LVTH162245-EP PDF预览

SN74LVTH162245-EP

更新时间: 2024-09-10 12:21:39
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
12页 348K
描述
3.3-V ABT 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SN74LVTH162245-EP 数据手册

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ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ ꢊꢃꢋ ꢌꢍ ꢎ  
ꢏ ꢐꢏ ꢌꢅ ꢑꢒꢆ ꢈ ꢉ ꢌꢒꢓ ꢆ ꢒꢔꢀ ꢆ ꢕꢑꢁꢀ ꢖꢍ ꢓ ꢅꢍ ꢕ  
ꢗ ꢓꢆ ꢇ ꢏ ꢌꢀꢆꢑꢆ ꢍ ꢘ ꢔꢆ ꢎꢔ ꢆꢀ  
SCBS782A − NOVEMBER 2003 − JULY 2006  
D
D
D
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
− 1000-V Charged-Device Model (C101)  
Enhanced Product-Change Notification  
Qualification Pedigree  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
WidebusFamily  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
D
A-Port Outputs Have Equivalent 22-Ω  
Series Resistors, So No External Resistors  
Are Required  
1DIR  
1B1  
1B2  
GND  
1B3  
1B4  
1OE  
1A1  
1A2  
GND  
1A3  
1A4  
2
3
4
D
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
5
6
3.3-V V  
)
CC  
7
V
V
CC  
CC  
D
D
D
D
Supports Unregulated Battery Operation  
Down to 2.7 V  
8
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
9
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
= 3.3 V, T = 25°C  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
D
D
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
V
V
CC  
CC  
2B5  
2B6  
GND  
2B7  
2B8  
2A5  
2A6  
GND  
2A7  
2A8  
Flow-Through Architecture Optimizes PCB  
Layout  
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
2DIR 24  
25 2OE  
description/ordering information  
The SN74LVTH162245 is a 16-bit (dual-octal) noninverting 3-state transceiver designed for low-voltage (3.3-V)  
operation, but with the capability to provide a TTL interface to a 5-V system environment.  
V
CC  
This device can be used as two 8-bit transceivers or one 16-bit transceiver. The device allows data transmission  
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control  
(DIR) input. The output-enable (OE) input can be used to disable the device so that the buses effectively are  
isolated.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
ꢆꢥ  
Copyright 2006 Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢮ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢐ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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