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SN74LVT574PWR PDF预览

SN74LVT574PWR

更新时间： 2024-11-05 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
15页 468K
描述
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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中文翻译

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SN74LVT574PWR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20,.25针数：20
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：0.85
其他特性：BROADSIDE VERSION OF 374; INPUTS CAN BE DRIVEN BY 3.3/5V DEVICES; BUS HOLD INPUTS控制类型：INDEPENDENT CONTROL
计数方向：UNIDIRECTIONAL系列：LVT
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：6.5 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：150000000 Hz
最大I（ol）：0.024 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：12 mAProp。Delay @ Nom-Sup：6.1 ns
传播延迟（tpd）：6.6 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：4.4 mm
Base Number Matches：1

SN74LVT574PWR 数据手册

 浏览型号SN74LVT574PWR的Datasheet PDF文件第2页浏览型号SN74LVT574PWR的Datasheet PDF文件第3页浏览型号SN74LVT574PWR的Datasheet PDF文件第4页浏览型号SN74LVT574PWR的Datasheet PDF文件第5页浏览型号SN74LVT574PWR的Datasheet PDF文件第6页浏览型号SN74LVT574PWR的Datasheet PDF文件第7页 
SN54LVT574, SN74LVT574  
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS139D – MAY 1992 – REVISED JULY 1995  
SN54LVT574 . . . J OR W PACKAGE  
SN74LVT574 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static Power  
Dissipation  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
13 7Q  
12 8Q  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
11  
GND  
CLK  
SN54LVT574 . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
Support Live Insertion  
3
2
1
20 19  
18  
4
5
6
7
8
3D  
4D  
5D  
6D  
7D  
2Q  
3Q  
4Q  
5Q  
6Q  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Packages, and Ceramic  
(J) DIPs  
17  
16  
15  
14  
9 10 11 12 13  
description  
These octal flip-flops are designed specifically for low-voltage (3.3-V) V  
provide a TTL interface to a 5-V system environment.  
operation, but with the capability to  
CC  
The eight flip-flops of the ′LVT574 are edge-triggered D-type flip-flops. On the positive transition of the clock  
(CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops.  
Old data can be retained or new data can be entered while the outputs are in the high-impedance state.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN74LVT574 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LVT574 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LVT574 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

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SN74LVT574PWR 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVT574PW TI

完全替代

 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVTH574PWR TI

类似代替

 3.3V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
SN74LVTH574PW TI

类似代替

 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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