Datasheet > 逻辑 > 总线驱动器/收发器> SN74LVT574NSR

SN74LVT574NSR

更新时间： 2024-11-08 23:06:23

品牌	Logo	应用领域
德州仪器 - TI		总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件信息通信管理
页数	文件大小	规格书
15页	468K
描述
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN74LVT574NSR 技术参数

是否无铅：	含铅	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOP,
针数：	20	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.51
系列：	LVT	JESD-30 代码：	R-PDSO-G20
长度：	12.6 mm	逻辑集成电路类型：	BUS DRIVER
位数：	8	功能数量：	1
端口数量：	2	端子数量：	20
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
传播延迟（tpd）：	6.6 ns	认证状态：	Not Qualified
座面最大高度：	2 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2.7 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	BICMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	5.3 mm	Base Number Matches：	1

SN74LVT574NSR 数据手册

SN54LVT574, SN74LVT574

3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCBS139D – MAY 1992 – REVISED JULY 1995

SN54LVT574 . . . J OR W PACKAGE

SN74LVT574 . . . DB, DW, OR PW PACKAGE

(TOP VIEW)

State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low Static Power

Dissipation

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V V

)

Support Unregulated Battery Operation

Down to 2.7 V

Typical V

< 0.8 V at V

(Output Ground Bounce)

OLP

= 3.3 V, T = 25°C

13 7Q

12 8Q

ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

GND

CLK

SN54LVT574 . . . FK PACKAGE

(TOP VIEW)

Latch-Up Performance Exceeds 500 mA

Per JEDEC Standard JESD-17

Bus-Hold Data Inputs Eliminate the Need

for External Pullup Resistors

Support Live Insertion

20 19

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK),

Ceramic Flat (W) Packages, and Ceramic

(J) DIPs

9 10 11 12 13

description

These octal flip-flops are designed specifically for low-voltage (3.3-V) V

provide a TTL interface to a 5-V system environment.

operation, but with the capability to

The eight flip-flops of the ′LVT574 are edge-triggered D-type flip-flops. On the positive transition of the clock

(CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus

lines without need for interface or pullup components. OE does not affect the internal operations of the flip-flops.

Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVT574 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count

and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN54LVT574 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74LVT574 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...15

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与SN74LVT574NSR相关器件

型号	品牌	获取价格	描述	数据表
SN74LVT574PW	TI	获取价格	3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVT574PWLE	TI	获取价格	3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVT574PWR	TI	获取价格	3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVT574PWRE4	TI	获取价格	3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVT639DW	TI	获取价格	LVT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20
SN74LVT639DWR	TI	获取价格	LVT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20
SN74LVT646	TI	获取价格	3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN74LVT646DB	TI	获取价格	3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN74LVT646DBLE	TI	获取价格	3.3-V ABT Octal Bus Transceivers And Registers With 3-State Outputs 24-SSOP -40 to 85
SN74LVT646DW	TI	获取价格	3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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