5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74LVT543DWE4
SN74LVT543DWE4 PDF预览

SN74LVT543DWE4

更新时间： 2024-09-14 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
13页 333K
描述
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN74LVT543DWE4 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP24,.4针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.32控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：LVT
JESD-30 代码：R-PDSO-G24长度：15.4 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.064 A
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE电源：3.3 V
Prop。Delay @ Nom-Sup：4.7 ns传播延迟（tpd）：7.3 ns
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
翻译：N/A宽度：7.5 mm
Base Number Matches：1

SN74LVT543DWE4 数据手册

 浏览型号SN74LVT543DWE4的Datasheet PDF文件第2页浏览型号SN74LVT543DWE4的Datasheet PDF文件第3页浏览型号SN74LVT543DWE4的Datasheet PDF文件第4页浏览型号SN74LVT543DWE4的Datasheet PDF文件第5页浏览型号SN74LVT543DWE4的Datasheet PDF文件第6页浏览型号SN74LVT543DWE4的Datasheet PDF文件第7页 
SN54LVT543, SN74LVT543  
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS137D – MAY 1992 – REVISED JULY 1995  
SN54LVT543 . . . JT PACKAGE  
SN74LVT543 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static Power  
Dissipation  
LEBA  
OEBA  
A1  
1
2
3
4
5
6
7
8
9
10  
24  
V
CC  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
23 CEBA  
22 B1  
21 B2  
20 B3  
19 B4  
18 B5  
17 B6  
16 B7  
)
CC  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Support Unregulated Battery Operation  
Down to 2.7 V  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
15  
B8  
CEAB 11  
GND 12  
14 LEAB  
13 OEAB  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
SN54LVT543 . . . FK PACKAGE  
(TOP VIEW)  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
Support Live Insertion  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK), and  
Ceramic (JT) DIPs  
4
3
2
1
28 27 26  
25  
A2  
A3  
A4  
NC  
A5  
A6  
A7  
B2  
B3  
B4  
5
24  
23  
6
7
22 NC  
21 B5  
20 B6  
19 B7  
8
description  
9
10  
11  
Theseoctaltransceiversaredesignedspecifically  
for low-voltage (3.3-V) V operation, but with the  
CC  
12 13 14 15 16 17 18  
capability to provide a TTL interface to a 5-V  
system environment.  
The ’LVT543 contain two sets of D-type latches for  
temporary storage of data flowing in either  
direction. Separate latch-enable (LEAB or LEBA)  
and output-enable (OEAB or OEBA) inputs are  
provided for each register to permit independent  
control in either direction of data flow.  
NC – No internal connection  
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB  
is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts  
the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect  
the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA,  
LEBA, and OEBA inputs.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1995, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

中文翻译

下载PDF

与SN74LVT543DWE4相关器件

型号 品牌 获取价格 描述 数据表
SN74LVT543DWR TI

获取价格

 		3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVT543DWRE4 TI

获取价格

 		3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVT543NSR TI

获取价格

 		3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVT543PW TI

获取价格

 		3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVT543PWLE TI

获取价格

 		3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVT543PWR TI

获取价格

 		3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVT543PWRE4 TI

获取价格

 		3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVT573 TI

获取价格

 		3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LVT573DB TI

获取价格

 		3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LVT573DBLE TI

获取价格

 		3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

与SN74LVT543DWE4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证