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SN74LVT244APW PDF预览

SN74LVT244APW

更新时间: 2024-11-18 12:15:07
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
13页 381K
描述
3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SN74LVT244APW 技术参数

生命周期:Obsolete包装说明:TSSOP, TSSOP20,.25
Reach Compliance Code:unknown风险等级:5.17
系列:LVTJESD-30 代码:R-PDSO-G20
长度:6.5 mm逻辑集成电路类型:BUS DRIVER
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):5.2 ns
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

SN74LVT244APW 数据手册

 浏览型号SN74LVT244APW的Datasheet PDF文件第2页浏览型号SN74LVT244APW的Datasheet PDF文件第3页浏览型号SN74LVT244APW的Datasheet PDF文件第4页浏览型号SN74LVT244APW的Datasheet PDF文件第5页浏览型号SN74LVT244APW的Datasheet PDF文件第6页浏览型号SN74LVT244APW的Datasheet PDF文件第7页 
SN54LVT244, SN74LVT244  
3.3-V ABT OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCBS135B – AUGUST 1992 – REVISED MARCH 1994  
SN54LVT244 . . . J OR W PACKAGE  
SN74LVT244 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static Power  
Dissipation  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Support Mixed-Mode Signal Operation (5-V  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
Input and Output Voltages With 3.3-V V  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V  
= 3.3 V, T = 25°C  
CC  
A
13 2A2  
12 1Y4  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model (C = 200 pF,  
R = 0)  
11  
2A1  
SN54LVT244 . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
Supports Live Insertion  
3
2
1
20 19  
18  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flatpacks (W), and Ceramic  
DIPS (J)  
17  
16  
15  
14  
9 10 11 12 13  
description  
These octal buffers and line drivers are designed specifically for low-voltage (3.3-V) V operation, but with the  
CC  
capability to provide a TTL interface to a 5-V system environment.  
The ’LVT244 is organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low,  
the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the  
high-impedance state.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN74LVT244 is packaged in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LVT244 is characterized for operation over the full military temperature range of 55°C to 125°C. The  
SN74LVT244 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
LVT244–5  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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