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SN74LVT16543DGG

更新时间： 2024-11-08 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
8页 147K
描述
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN74LVT16543DGG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete包装说明：TSSOP,
Reach Compliance Code：compliant风险等级：5.33
其他特性：INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH系列：LVT
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：14 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER湿度敏感等级：1
位数：8功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：250最大电源电流（ICC）：5 mA
传播延迟（tpd）：7.8 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：6.1 mmBase Number Matches：1

SN74LVT16543DGG 数据手册

 浏览型号SN74LVT16543DGG的Datasheet PDF文件第2页浏览型号SN74LVT16543DGG的Datasheet PDF文件第3页浏览型号SN74LVT16543DGG的Datasheet PDF文件第4页浏览型号SN74LVT16543DGG的Datasheet PDF文件第5页浏览型号SN74LVT16543DGG的Datasheet PDF文件第6页浏览型号SN74LVT16543DGG的Datasheet PDF文件第7页 
SN54LVT16543, SN74LVT16543  
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS148C – MAY 1992 – REVISED JULY 1995  
SN54LVT16543 . . . WD PACKAGE  
SN74LVT16543 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
1OEAB  
1LEAB  
1CEAB  
GND  
1OEBA  
1LEBA  
1CEBA  
GND  
1B1  
1B2  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
Members of the Texas Instruments  
Widebus Family  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
)
1A1  
1A2  
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
V
V
CC  
CC  
1A3  
1A4  
1B3  
1B4  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
1A5 10  
47 1B5  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
GND  
1A6  
GND  
1B6  
11  
12  
46  
45  
1A7 13  
1A8 14  
2A1 15  
2A2 16  
2A3 17  
GND 18  
2A4 19  
2A5 20  
2A6 21  
44 1B7  
43 1B8  
42 2B1  
41 2B2  
40 2B3  
39 GND  
38 2B4  
37 2B5  
36 2B6  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
Support Live Insertion  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
V
22  
35  
V
CC  
CC  
Flow-Through Architecture Optimizes  
PCB Layout  
2A7 23  
34 2B7  
2A8 24  
33 2B8  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
GND 25  
32 GND  
31 2CEBA  
30 2LEBA  
29 2OEBA  
2CEAB 26  
2LEAB 27  
2OEAB 28  
description  
The ’LVT16543 are 16-bit registered transceivers designed for low-voltage (3.3-V) V  
operation, but with the  
CC  
capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit  
transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or  
OEBA) inputs are provided for each register to permit independent control in either direction of data flow.  
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB  
is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts  
the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect  
the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA,  
LEBA, and OEBA inputs.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1995, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

中文翻译

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SN74LVT16543DGG 替代型号

型号 品牌 替代类型 描述 数据表
V62/04715-01XE TI

完全替代

 3.3-V ABT 16-BIT REGISTERED TRANSCEIVER 3-STATE OUTPUTS
CLVTH16543IDGGREP TI

完全替代

 3.3-V ABT 16-BIT REGISTERED TRANSCEIVER 3-STATE OUTPUTS
SN74LVTH16543DGG TI

完全替代

 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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 		3.3-V ABT 16-Bit Registered Transceivers With 3-State Outputs 56-TSSOP -40 to 85
SN74LVT16543DL TI

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 		3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVT16543DLG4 TI

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 		3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVT16543DLR TI

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 		3.3-V ABT 16-Bit Registered Transceivers With 3-State Outputs 56-SSOP -40 to 85
SN74LVT16543DLRG4 TI

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 		3.3-V ABT 16-Bit Registered Transceivers With 3-State Outputs 56-SSOP -40 to 85
SN74LVT16601DGGR TI

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 		LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74LVT16601DL TI

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 		LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74LVT16611DGG TI

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 		LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74LVT16611DGGR TI

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 		LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74LVT16611DLR TI

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 		LVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56

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