SN54LVT16240, SN74LVT16240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS717A–APRIL 2000–REVISED NOVEMBER 2006
FEATURES
•
Members of the Texas Instruments Widebus™
Family
SN54LVT16240 . . . WD PACKAGE
SN74LVT16240 . . . DGG OR DL PACKAGE
(TOP VIEW)
•
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation
1OE
1Y1
1Y2
GND
1Y3
1Y4
1
2
3
4
5
6
7
8
9
10
48 2OE
47 1A1
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•
•
•
•
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Support Mixed-Mode Signal Operation (5-V
46
1A2
Input and Output Voltages With 3.3-V VCC
)
45 GND
44 1A3
43 1A4
Support Unregulated Battery Operation Down
to 2.7 V
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
V
CC
42
41
40
39
V
CC
2Y1
2Y2
GND
2A1
2A2
GND
Ioff and Power-Up 3-State Support Hot
Insertion
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
2Y3 11
2Y4 12
3Y1 13
38 2A3
37 2A4
36 3A1
Flow-Through Architecture Optimizes PCB
Layout
14
15
16
17
18
19
20
21
22
23
24
35
34
33
32
31
30
29
28
27
26
25
3Y2
GND
3Y3
3A2
GND
3A3
3A4
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
3Y4
ESD Protection Exceeds JESD 22
V
CC
V
CC
–
–
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2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
4Y1
4Y2
GND
4Y3
4Y4
4OE
4A1
4A2
GND
4A3
4A4
3OE
1000-V Charged-Device Model (C101)
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Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package Using
25-mil Center-to-Center Spacings
DESCRIPTION/ORDERING INFORMATION
The 'LVT16240 devices are 16-bit buffers and line drivers designed specifically for low-voltage (3.3-V) VCC
operation, but with the capability to provide a TTL interface to a 5-V system environment.
These devices are designed specifically to improve both the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
The devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The devices provide
inverting outputs and symmetrical active-low output-enable (OE) inputs.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.