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SN74LVT16240 PDF预览

SN74LVT16240

更新时间： 2024-11-04 23:03:19
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
10页 167K
描述
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN74LVT16240 数据手册

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SN54LVT16240, SN74LVT16240  
3.3-V ABT 16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCBS717 – APRIL 2000  
SN54LVT16240 . . . WD PACKAGE  
SN74LVT16240 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
1OE  
1Y1  
1Y2  
GND  
1Y3  
1Y4  
1
2
3
4
5
6
7
8
9
48 2OE  
47 1A1  
46 1A2  
45 GND  
44 1A3  
43 1A4  
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
V
42  
V
CC  
CC  
2Y1  
2Y2  
41 2A1  
40 2A2  
39 GND  
38 2A3  
37 2A4  
36 3A1  
35 3A2  
34 GND  
33 3A3  
32 3A4  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
GND 10  
2Y3 11  
2Y4 12  
3Y1 13  
3Y2 14  
GND 15  
3Y3 16  
3Y4 17  
= 3.3 V, T = 25°C  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
Flow-Through Architecture Optimizes PCB  
Layout  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
V
18  
31  
V
CC  
CC  
4Y1 19  
4Y2 20  
GND 21  
4Y3 22  
30 4A1  
29 4A2  
28 GND  
27 4A3  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
23  
24  
26  
25  
4Y4  
4OE  
4A4  
3OE  
– 1000-V Charged-Device Model (C101)  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
The ’LVT16240 devices are 16-bit buffers and line drivers designed specifically for low-voltage (3.3-V) V  
operation, but with the capability to provide a TTL interface to a 5-V system environment.  
CC  
These devices are designed specifically to improve both the performance and density of 3-state memory  
address drivers, clock drivers, and bus-oriented receivers and transmitters.  
The devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The devices provide  
inverting outputs and symmetrical active-low output-enable (OE) inputs.  
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
through a pullup resistor;  
CC  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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