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SN74LVT162245ADLG4

更新时间： 2024-09-13 05:16:59
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
18页 581K
描述
3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN74LVT162245ADLG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP48,.4针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.15
Is Samacsys：N其他特性：PORT A WITH SERIES RESISTORS
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：LVTJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：15.875 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.064 A湿度敏感等级：1
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP48,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TUBE
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：4 ns传播延迟（tpd）：4.6 ns
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：7.49 mm
Base Number Matches：1

SN74LVT162245ADLG4 数据手册

 浏览型号SN74LVT162245ADLG4的Datasheet PDF文件第2页浏览型号SN74LVT162245ADLG4的Datasheet PDF文件第3页浏览型号SN74LVT162245ADLG4的Datasheet PDF文件第4页浏览型号SN74LVT162245ADLG4的Datasheet PDF文件第5页浏览型号SN74LVT162245ADLG4的Datasheet PDF文件第6页浏览型号SN74LVT162245ADLG4的Datasheet PDF文件第7页 
SN54LVT162245A, SN74LVT162245A  
3.3-V ABT 16-BIT BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS714D–FEBRUARY 2000–REVISED NOVEMBER 2006  
FEATURES  
SN54LVT162245A. . . WD PACKAGE  
SN74LVT162245A. . . DGG OR DL PACKAGE  
(TOP VIEW)  
•
Members of the Texas Instruments Widebus™  
Family  
•
A-Port Outputs Have Equivalent 22-Ω Series  
Resistors, So No External Resistors Are  
Required  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1DIR  
1B1  
1B2  
GND  
1B3  
1B4  
1OE  
1A1  
1A2  
GND  
1A3  
1A4  
2
3
•
•
•
•
•
•
•
•
Supprt Mixed-Mode Signal Operation (5-V  
4
Input and Output Voltages With 3.3-V VCC  
)
5
Support Unregulated Battery Operation Down  
to 2.7 V  
6
7
V
CC  
V
CC  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
8
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Ioff and Power-Up 3-State Support Hot  
Insertion  
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
Flow-Through Architecture Optimizes PCB  
Layout  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
V
CC  
V
CC  
ESD Protection Exceeds JESD 22  
2B5  
2B6  
GND  
2B7  
2B8  
2DIR  
2A5  
2A6  
GND  
2A7  
2A8  
2OE  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
The 'LVT162245A devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage  
(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.  
These devices are designed for asynchronous communication between two data buses. The logic levels of the  
direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port  
outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to  
the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are  
activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level  
applied to prevent excess ICC and ICCZ  
.
The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors  
to reduce overshoot and undershoot.  
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry  
disables the outputs, preventing damaging current backflow through the devices when they are powered down.  
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
UNLESS OTHERWISE NOTED this document contains  
Copyright © 2000–2006, Texas Instruments Incorporated  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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