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SN74LVCR16245ADL

更新时间： 2024-10-30 22:56:23
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
12页 332K
描述
16 BIT BUS TRANSCEIVER WITH 3 STATE OUTPUTS

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中文翻译

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SN74LVCR16245ADL 数据手册

 浏览型号SN74LVCR16245ADL的Datasheet PDF文件第2页浏览型号SN74LVCR16245ADL的Datasheet PDF文件第3页浏览型号SN74LVCR16245ADL的Datasheet PDF文件第4页浏览型号SN74LVCR16245ADL的Datasheet PDF文件第5页浏览型号SN74LVCR16245ADL的Datasheet PDF文件第6页浏览型号SN74LVCR16245ADL的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅꢆꢇ ꢈꢉ ꢊꢃ ꢋꢌ  
ꢈ ꢉ ꢍꢎꢏ ꢐ ꢎꢑꢀ ꢐ ꢇꢌꢁ ꢀꢆ ꢒ ꢏꢅ ꢒ ꢇ  
ꢓ ꢏꢐ ꢔ ꢕ ꢍꢀꢐꢌꢐ ꢒ ꢖ ꢑꢐ ꢗꢑ ꢐꢀ  
SCES427A − FEBRUARY 2003 − REVISED NOVEMBER 2004  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
D
Member of the Texas Instruments  
WidebusFamily  
D
D
D
D
D
D
Operates From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1DIR  
1B1  
1B2  
GND  
1B3  
1B4  
1OE  
1A1  
1A2  
GND  
1A3  
1A4  
2
Max t of 4.8 ns at 3.3 V  
pd  
3
4
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
5
= 3.3 V, T = 25°C  
A
6
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
7
V
V
CC  
CC  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
8
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
3.3-V V  
)
CC  
D
All Inputs and Outputs Have Equivalent  
26-Ω Series Resistors, So No External  
Resistors Are Required  
D
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
V
V
CC  
CC  
2B5  
2B6  
GND  
2B7  
2B8  
2A5  
2A6  
GND  
2A7  
2A8  
2OE  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
description/ordering information  
2DIR  
This 16-bit (dual-octal) noninverting bus  
transceiver is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74LVCR16245A is designed for asynchronous communication between data buses. The  
control-function implementation minimizes external-timing requirements.  
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the  
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)  
input. The output-enable (OE) input can disable the device so that the buses are effectively isolated.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube  
SN74LVCR16245ADL  
SSOP − DL  
LVCR16245A  
Tape and reel SN74LVCR16245ADLR  
Tape and reel SN74LVCR16245ADGGR  
Tape and reel SN74LVCR16245ADGVR  
TSSOP − DGG  
LVCR16245A  
LDR245A  
−40°C to 85°C  
TVSOP − DGV  
VFBGA − GQL  
SN74LVCR16245AGQLR  
Tape and reel  
LDR245A  
VFBGA − ZQL (Pb-free)  
SN74LVCR16245AZQLR  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
ꢗꢇ ꢖ ꢘꢑ ꢆ ꢐꢏ ꢖ ꢁ ꢘ ꢌꢐꢌ ꢙꢚ ꢛ ꢜꢝ ꢞ ꢟꢠ ꢙꢜꢚ ꢙꢡ ꢢꢣ ꢝ ꢝ ꢤꢚꢠ ꢟꢡ ꢜꢛ ꢥꢣꢦ ꢧꢙꢢ ꢟꢠ ꢙꢜꢚ ꢨꢟ ꢠꢤ ꢩ  
ꢗꢝ ꢜ ꢨꢣꢢ ꢠ ꢡ ꢢ ꢜꢚ ꢛꢜ ꢝ ꢞ ꢠ ꢜ ꢡ ꢥꢤ ꢢ ꢙꢛ ꢙꢢꢟ ꢠꢙ ꢜꢚꢡ ꢥꢤ ꢝ ꢠꢪ ꢤ ꢠꢤ ꢝ ꢞꢡ ꢜꢛ ꢐꢤꢫ ꢟꢡ ꢏꢚꢡ ꢠꢝ ꢣꢞ ꢤꢚꢠ ꢡ  
ꢡ ꢠ ꢟ ꢚꢨ ꢟ ꢝꢨ ꢬ ꢟ ꢝꢝ ꢟ ꢚ ꢠꢭꢩ ꢗꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜꢚ ꢥꢝ ꢜꢢ ꢤꢡ ꢡꢙ ꢚꢮ ꢨꢜꢤ ꢡ ꢚꢜꢠ ꢚꢤ ꢢꢤ ꢡꢡ ꢟꢝ ꢙꢧ ꢭ ꢙꢚꢢ ꢧꢣꢨ ꢤ  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
Copyright 2004, Texas Instruments Incorporated  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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SN74LVCR16245ADL 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVCR16245ADLR TI

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