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SN74LVCHR16245A

更新时间： 2024-01-18 13:16:44
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
10页 140K
描述
16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74LVCHR16245A 数据手册

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SN74LVCHR16245A  
16-BIT BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCAS582G – NOVEMBER 1996 – REVISED JUNE 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1DIR  
1B1  
1B2  
GND  
1B3  
1B4  
1OE  
1A1  
1A2  
GND  
1A3  
1A4  
2
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
3
= 3.3 V, T = 25°C  
CC  
A
4
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
5
= 3.3 V, T = 25°C  
A
6
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
7
V
V
CC  
CC  
8
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
3.3-V V  
)
9
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Power Off Disables Inputs/Outputs,  
Permitting Live Insertion  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
V
V
CC  
CC  
2B5  
2B6  
GND  
2B7  
2B8  
2DIR  
2A5  
2A6  
GND  
2A7  
2A8  
2OE  
All Outputs Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
NOTE: For order entry:  
The DGG package is abbreviated to G.  
For tape and reel:  
The DGGR package is abbreviated to GR, and  
the DLR package is abbreviated to LR.  
description  
This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74LVCHR16245A is designed for asynchronous communication between data buses. The  
control-function implementation minimizes external-timing requirements.  
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the  
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)  
input. The output-enable (OE) input can disable the device so that the buses are effectively isolated.  
All outputs, which are designed to sink up to 12 mA, include equivalent 26- series resistors to reduce  
overshoot and undershoot.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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