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SN74LVCHR162245ALR PDF预览

SN74LVCHR162245ALR

更新时间： 2024-01-26 20:43:16
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 579K
描述
LVC/LCX/Z SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, 0.300 INCH, PLASTIC, SSOP-48

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SN74LVCHR162245ALR 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：0.300 INCH, PLASTIC, SSOP-48针数：48
Reach Compliance Code：unknown风险等级：5.38
Is Samacsys：N系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G48长度：15.875 mm
逻辑集成电路类型：BUS TRANSCEIVER位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH传播延迟（tpd）：5.7 ns
认证状态：Not Qualified座面最大高度：2.794 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL宽度：7.5 mm
Base Number Matches：1

SN74LVCHR162245ALR 数据手册

 浏览型号SN74LVCHR162245ALR的Datasheet PDF文件第2页浏览型号SN74LVCHR162245ALR的Datasheet PDF文件第3页浏览型号SN74LVCHR162245ALR的Datasheet PDF文件第4页浏览型号SN74LVCHR162245ALR的Datasheet PDF文件第5页浏览型号SN74LVCHR162245ALR的Datasheet PDF文件第6页浏览型号SN74LVCHR162245ALR的Datasheet PDF文件第7页 
SN74LVCHR162245A  
16-BIT BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCAS582E – NOVEMBER 1996 – REVISED JUNE 1998  
G OR L PACKAGE  
(TOP VIEW)  
D
D
D
D
D
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1DIR  
1B1  
1B2  
GND  
1B3  
1B4  
1OE  
1A1  
1A2  
GND  
1A3  
1A4  
2
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
3
= 3.3 V, T = 25°C  
CC  
A
4
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
5
= 3.3 V, T = 25°C  
A
6
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
7
V
V
CC  
CC  
8
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
3.3-V V  
)
9
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
D
D
Power Off Disables Inputs/Outputs,  
Permitting Live Insertion  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
D
D
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
V
V
CC  
2B5  
CC  
2A5  
2A6  
GND  
2A7  
2A8  
2OE  
2B6  
GND  
2B7  
2B8  
2DIR  
D
D
All Outputs Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (L) and Thin Shrink  
Small-Outline (G) Packages  
NOTE: G is the abbreviated alias for the DGG package, and  
L is the abbreviated alias for the DL package.  
description  
This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74LVCHR162245A is designed for asynchronous communication between data buses. The  
control-function implementation minimizes external timing requirements.  
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the  
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)  
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.  
All outputs, which are designed to sink up to 12 mA, include equivalent 26-W resistors to reduce overshoot and  
undershoot.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
5–155  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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