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SN74LVCH32374A_16

更新时间： 2024-11-27 02:58:47
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德州仪器 - TI /
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9页 133K
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32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

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SN74LVCH32374A  
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCAS619A – OCTOBER 1998 – REVISED JUNE 1999  
Member of the Texas Instruments  
Widebus Family  
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input and Output Voltages  
With 3.3-V V  
)
CC  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
= 3.3 V, T = 25°C  
OLP  
CC  
A
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Packaged in Plastic Fine-Pitch Ball Grid  
Array Package  
Power Off Disables Outputs, Permitting  
Live Insertion  
description  
This 32-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74LVCH32374A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus  
drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop.  
On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up  
at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without interface or pullup components.  
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74LVCH32374A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
CLK  
D
H
L
OE  
L
↑
↑
H
L
L
L
H or L  
X
X
X
Q
0
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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