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SN74LVCH32373AGKE

更新时间： 2024-11-22 22:05:27
品牌 Logo 应用领域
德州仪器 - TI 锁存器逻辑集成电路输出元件输入元件驱动
页数 文件大小 规格书
9页 133K
描述
32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74LVCH32373AGKE 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：PLASTIC, FBGA-96
针数：96Reach Compliance Code：not_compliant
风险等级：5.44Is Samacsys：N
其他特性：BUS HOLD INPUTS ELIMINATE THE NEED FOR EXTERNAL PULLUP/PULLDOWN RESISTORS系列：LVC/LCX/Z
JESD-30 代码：R-PBGA-B96长度：13.5 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.024 A位数：8
功能数量：4端口数量：2
端子数量：96最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装等效代码：BGA96,6X16,32
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
Prop。Delay @ Nom-Sup：4.2 ns传播延迟（tpd）：5.3 ns
认证状态：Not Qualified座面最大高度：1.4 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.5 mm
Base Number Matches：1

SN74LVCH32373AGKE 数据手册

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SN74LVCH32373A  
32-BIT TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCAS618A – OCTOBER 1998 – REVISED JUNE 1999  
Member of the Texas Instruments  
Widebus Family  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Packaged in Plastic Fine-Pitch Ball Grid  
Array Package  
Power Off Disables Outputs, Permitting  
Live Insertion  
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
description  
This 32-bit transparent D-type latch is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74LVCH32373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus  
drivers, and working registers. It can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When  
the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs  
are latched at the levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without interface or pullup components.  
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74LVCH32373A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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