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SN74LVCH32373A

更新时间： 2024-11-25 22:36:07

品牌	Logo	应用领域
德州仪器 - TI		锁存器输出元件
页数	文件大小	规格书
9页	133K
描述
32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74LVCH32373A 数据手册

SN74LVCH32373A

32-BIT TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCAS618A – OCTOBER 1998 – REVISED JUNE 1999

Member of the Texas Instruments

Widebus Family

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

EPIC (Enhanced-Performance Implanted

CMOS) Submicron Process

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Typical V

< 0.8 V at V

(Output Ground Bounce)

OLP

= 3.3 V, T = 25°C

Latch-Up Performance Exceeds 250 mA Per

JESD 17

Typical V

> 2 V at V

(Output V

Undershoot)

OHV

= 3.3 V, T = 25°C

Packaged in Plastic Fine-Pitch Ball Grid

Array Package

Power Off Disables Outputs, Permitting

Live Insertion

Supports Mixed-Mode Signal Operation

(5-V Input and Output Voltages With

3.3-V V

)

description

This 32-bit transparent D-type latch is designed for 1.65-V to 3.6-V V

operation.

The SN74LVCH32373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus

drivers, and working registers. It can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When

the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs

are latched at the levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive

thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines

without interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74LVCH32373A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...9

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与SN74LVCH32373A相关器件

型号	品牌	获取价格	描述	数据表
SN74LVCH32373AGKE	TI	获取价格	32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74LVCH32373ANMJR	TI	获取价格	具有三态输出的 32 位透明 D 型锁存器 \| NMJ \| 96 \| -40 to 85
SN74LVCH32373AZKER	TI	获取价格	32-Bit Transparent D-Type Latch With 3-State Outputs 96-LFBGA -40 to 85
SN74LVCH32374A	TI	获取价格	32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVCH32374A_16	TI	获取价格	32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74LVCH32374AGKE	TI	获取价格	32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVCH32374AGKER	TI	获取价格	32-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 96-LFBGA -40 to 85
SN74LVCH32374AZKER	TI	获取价格	32-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 96-LFBGA -40 to 85
SN74LVCH8T245	TI	获取价格	8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUT
SN74LVCH8T245_10	TI	获取价格	8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUT

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