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SN74LVCH32244AGKE

更新时间： 2024-11-22 22:05:27
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
9页 133K
描述
32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

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SN74LVCH32244AGKE 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：LFBGA, BGA96(UNSPEC)针数：96
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.45控制类型：ENABLE LOW
系列：LVC/LCX/ZJESD-30 代码：R-PBGA-B96
长度：13.5 mm逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.024 A位数：4
功能数量：8端口数量：2
端子数量：96最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装等效代码：BGA96(UNSPEC)
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
电源：3.3 V传播延迟（tpd）：4.7 ns
认证状态：Not Qualified座面最大高度：1.4 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
宽度：5.5 mmBase Number Matches：1

SN74LVCH32244AGKE 数据手册

 浏览型号SN74LVCH32244AGKE的Datasheet PDF文件第2页浏览型号SN74LVCH32244AGKE的Datasheet PDF文件第3页浏览型号SN74LVCH32244AGKE的Datasheet PDF文件第4页浏览型号SN74LVCH32244AGKE的Datasheet PDF文件第5页浏览型号SN74LVCH32244AGKE的Datasheet PDF文件第6页浏览型号SN74LVCH32244AGKE的Datasheet PDF文件第7页 
SN74LVCH32244A  
32-BIT BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
SCAS617A – OCTOBER 1998 – REVISED JUNE 1999  
Member of the Texas Instruments  
Widebus Family  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Packaged in Plastic Fine-Pitch Ball Grid  
Array Package  
I
Supports Partial-Power-Down-Mode  
off  
Operation  
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
3.3-V V  
)
CC  
description  
This 32-bit buffer/driver is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74LVCH32244A is designed specifically to improve the performance and density of 3-state memory  
address drivers, clock drivers, and bus-oriented receivers and transmitters.  
Thedevicecanbeusedaseight4-bitbuffers, four8-bitbuffers, two16-bitbuffers, orone32-bitbuffer. Itprovides  
true outputs and symmetrical active-low output-enable (OE) inputs.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74LVCH32244A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each 4-bit buffer)  
INPUTS  
OUTPUT  
Y
A
OE  
L
H
L
H
L
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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