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SN74LVCH245ARGYR PDF预览

SN74LVCH245ARGYR

更新时间： 2024-11-23 05:16:59
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
27页 1093K
描述
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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中文翻译

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SN74LVCH245ARGYR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC20/24,.14X.18,20针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.11
其他特性：WITH DIRECTION CONTROL控制类型：COMMON CONTROL
计数方向：BIDIRECTIONAL系列：LVC/LCX/Z
JESD-30 代码：R-PQCC-N20JESD-609代码：e4
长度：4.5 mm逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.024 A湿度敏感等级：2
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装等效代码：LCC20/24,.14X.18,20封装形状：RECTANGULAR
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.01 mAProp。Delay @ Nom-Sup：6.3 ns
传播延迟（tpd）：7.3 ns认证状态：Not Qualified
施密特触发器：No座面最大高度：1 mm
子类别：Bus Driver/Transceiver最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：3.5 mm
Base Number Matches：1

SN74LVCH245ARGYR 数据手册

 浏览型号SN74LVCH245ARGYR的Datasheet PDF文件第2页浏览型号SN74LVCH245ARGYR的Datasheet PDF文件第3页浏览型号SN74LVCH245ARGYR的Datasheet PDF文件第4页浏览型号SN74LVCH245ARGYR的Datasheet PDF文件第5页浏览型号SN74LVCH245ARGYR的Datasheet PDF文件第6页浏览型号SN74LVCH245ARGYR的Datasheet PDF文件第7页 
SN54LVCH245A, SN74LVCH245A  
OCTAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES008O–JULY 1995–REVISED DECEMBER 2005  
FEATURES  
•
•
•
•
Operate From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 6.3 ns at 3.3 V  
•
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
•
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Support Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With  
3.3-V VCC  
)
SN54LVCH245A . . . J OR W PACKAGE  
SN74LVCH245A . . . DB, DGV, DW, NS,  
OR PW PACKAGE  
SN74LVCH245A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LVCH245A . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
20  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIR  
A1  
A2  
A3  
A4  
V
CC  
3
2
1
20 19  
18  
B1  
B2  
B3  
B4  
B5  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
2
3
4
5
6
7
8
9
19  
18  
17  
16  
15  
14  
13  
12  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
17  
16  
15  
14  
A5  
A6  
A7  
A8  
9
10 11 12 13  
10  
11  
GND  
DESCRIPTION/ORDERING INFORMATION  
The SN54LVCH245A octal bus transceiver is designed for 2.7-V to 3.6-V VCC operation, and the  
SN74LVCH245A octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
These devices are designed for asynchronous communication between data buses. These devices transmit data  
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control  
(DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated.  
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the  
outputs, preventing damaging current backflow through the devices when they are powered down.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or  
pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input  
circuit and is not disabled by OE or DIR.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
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中文翻译

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SN74LVCH245ARGYR 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVCH245ARGYRG4 TI

完全替代

 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVC245ARGYRG4 TI

类似代替

 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74LVC245ARGYR TI

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 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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