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SN74LVCH245 PDF预览

SN74LVCH245

更新时间： 2024-02-03 16:24:05
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
7页 108K
描述
OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74LVCH245 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20,.25针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.16其他特性：WITH DIRECTION CONTROL
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G20
长度：6.5 mm逻辑集成电路类型：BUS TRANSCEIVER
位数：4功能数量：2
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：8 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.7 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

SN74LVCH245 数据手册

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SN74LVCH245  
OCTAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCES008 – JULY 1995  
DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIR  
A1  
A2  
A3  
A4  
V
CC  
= 3.3 V, T = 25°C  
CC  
A
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
OH  
= 3.3 V, T = 25°C  
CC  
A
ESD Protection Exceeds 2000 V Per  
MIL-STD-833C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
A5  
A6  
A7  
A8  
GND  
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltages With  
3.3-VV  
)
CC  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup Resistors  
Package Options Include Shrink  
Small-Outline (DB), Plastic Small-Outline  
(DW), and Thin Shrink Small-Outline (PW)  
Packages  
description  
This octal bus transceiver is designed for 2.7-V to 3.6-V V  
environment.  
operation; it can interface to a 5-V system  
CC  
The SN74LVCH245 is designed for asynchronous communication between data buses. The device transmits  
data from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the  
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are  
effectively isolated.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74LVCH245 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OPERATION  
OE  
L
DIR  
L
B data to A bus  
A data to B bus  
Isolation  
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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