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SN74LVCH16952ADGG

更新时间： 2024-09-14 23:06:23
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德州仪器 - TI 输出元件
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11页 169K
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16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74LVCH16952ADGG 数据手册

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SN74LVCH16952A  
16-BIT REGISTERED TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCAS320F – NOVEMBER 1993 – REVISED JUNE 1998  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1OEAB  
1CLKAB  
1CEAB  
GND  
1OEBA  
1CLKBA  
1CEBA  
GND  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
1A1  
1A2  
52 1B1  
51 1B2  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
V
50  
V
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
CC  
CC  
1A3  
1A4  
49 1B3  
48 1B4  
47 1B5  
46 GND  
45 1B6  
44 1B7  
43 1B8  
3.3-V V  
)
CC  
1A5 10  
GND 11  
1A6 12  
1A7 13  
1A8 14  
Power Off Disables Outputs, Permitting  
Live Insertion  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
V
V
CC  
CC  
2A7  
2A8  
GND  
2B7  
2B8  
GND  
2CEBA  
2CLKBA  
2OEBA  
description  
2CEAB  
2CLKAB  
2OEAB  
This 16-bit registered transceiver is designed for  
1.65-V to 3.6-V V operation.  
CC  
The SN74LVCH16952A contains two sets of  
D-type flip-flops for temporary storage of data  
flowing in either direction. It can be used as two  
8-bit transceivers or one 16-bit transceiver. Data  
on the A or B bus is stored in the registers on the  
low-to-high transition of the clock (CLKAB or  
CLKBA) input, provided that the clock-enable  
(CEAB or CEBA) input is low. Taking the  
output-enable (OEAB or OEBA) input low  
accesses the data on either port.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74LVCH16952A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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